An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. - Yung-Yuan Chen; Ching-Hwa Cheng; Yung-Ci Chou (EDCC, 1994)

An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. - Yung-Yuan Chen; Ching-Hwa Cheng; Jwu-E Chen (VLSI Design, 1995)

A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors. - Yung-Yuan Chen; Shambhu J. Upadhyaya; Ching-Hwa Cheng (IEEE Trans. Computers, 1997)

Charge Sharing Fault Detection for CMOS Domino Logic Circuits. - Ching-Hwa Cheng; Shih-Chieh Chang; Jinn-Shyan Wang; Wen-Ben Jone (DFT, 1999)

Charge sharing fault analysis and testing for CMOS domino logic circuits. - Ching-Hwa Cheng; Wen-Ben Jone; Jinn-Shyan Wang; Shih-Chieh Chang (Asian Test Symposium, 2000)

Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. - Ching-Hwa Cheng; Jinn-Shyan Wang; Shih-Chieh Chang; Wen-Ben Jone (DFT, 2000)

Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. - Ching-Hwa Cheng; Shih-Chieh Chang; Shin-De Li; Wen-Ben Jone; Jinn-Shyan Wang (ICCAD, 2000)

Charge-sharing alleviation and detection for CMOS domino circuits. - Shih-Chieh Chang; Ching-Hwa Cheng; Wen-Ben Jone; Shin-De Lee; Jinn-Shyan Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits. - Ching-Hwa Cheng (DFT, 2002)

Novel Techniques for Improving Testability Analysis. - Yin-He Su; Ching-Hwa Cheng; Shih-Chieh Chang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Design Scan Test Strategy for Single Phase Dynamic Circuits. - Ching-Hwa Cheng (DFT, 2003)

Noise-Aware Floorplanning for Fast Power Supply Network Design. - Chang-Tzu Lin; Tai-Wei Kung; De-Sheng Chen; Yiwen Wang 003; Ching-Hwa Cheng (ISCAS, 2007)

A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications. - Chih-Da Chien; Chien-Chang Lin; Yi-Hung Shih; He-Chun Chen; Chia-Jui Huang; Cheng-Yen Yu; Chih-Liang Chen; Ching-Hwa Cheng; Jiun-In Guo (ISSCC, 2007)

Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. - Hsiang-Hui Huang; Ching-Hwa Cheng (VTS, 2007)

Fixed-outline floorplanning using robust evolutionary search. - De-Sheng Chen; Chang-Tzu Lin; Yiwen Wang 003; Ching-Hwa Cheng (Eng. Appl. Artif. Intell., 2007)

An All-Digital High-Precision Built-In Delay Time Measurement Circuit. - Ming-Chien Tsai; Ching-Hwa Cheng; Chiou-Mao Yang (VTS, 2008)

A full-synthesizable high-precision built-in delay time measurement circuit. - Ming-Chien Tsai; Ching-Hwa Cheng (ASP-DAC, 2009)

CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. - Chin-Hsien Wang; Ching-Hwa Cheng; Jiun-In Guo (ASP-DAC, 2009)

Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test. - Chen-I Chung; Jyun-Sian Jhou; Ching-Hwa Cheng; Sih-Yan Li (Asian Test Symposium, 2009)

Design High-Performance and Low-Power Adder Cores with Full-Swing Nodes for Embedded Systems. - Ching-Hwa Cheng; Chiou-Kou Tung; Shao-Hui Shieh; Yu-Cherng Hung (IIH-MSP, 2009)

A Multi-standard Video Decoder for High Definition Video Applications. - Cheng-An Chien; Chih-Da Chien; Jui-Chin Chu; Jiun-In Guo; Ching-Hwa Cheng (ISCAS, 2009)

Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. - Chen-I Chung; Shuo-Wen Chang; Ching-Hwa Cheng (ITC, 2009)

CKVdd: A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits. - Ching-Hwa Cheng; Chin-Hsien Wang (IEICE Trans. Electron., 2009)

A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. - Chih-Da Chien; Cheng-An Chien; Jui-Chin Chu; Jiun-In Guo; Ching-Hwa Cheng (ACM Trans. Design Autom. Electr. Syst., 2009)

Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. - Chen-I Chung; Shuo-Wen Chang; Feng-Tso Chien; Ching-Hwa Cheng (ASP-DAC, 2010)

Built-in self at-speed delay binning and calibration mechanism in wireless test platform. - Chen-I Chung; Jyun-Sian Jhou; Ching-Hwa Cheng (ASP-DAC, 2010)

Dynamic voltage domain assignment technique for low power performance manageable cell based design. - Elone Lee; Feng-Tso Chien; Ching-Hwa Cheng; Jiun-In Guo (ASP-DAC, 2010)

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. - Cheng-An Chien; Yao-Chang Yang; Hsiu-Cheng Chang; Jia-Wei Chen; Cheng-Yen Chang; Jiun-In Guo; Jinn-Shyan Wang; Ching-Hwa Cheng (ASP-DAC, 2011)

Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. - Yu-Tzu Tsai; Cheng-Chih Tsai; Cheng-An Chien; Ching-Hwa Cheng; Jiun-In Guo (ASP-DAC, 2011)

A low-power management technique for high-performance domino circuits. - Yu-Tzu Tsai; Cheng-Chih Tsai; Cheng-An Chien; Ching-Hwa Cheng; Jiun-In Guo (ASP-DAC, 2011)

Built-in fine resolution clipping with calibration technique for high-speed testing by using wireless testers. - Ching-Hwa Cheng; Chen-I Chung (DSN Workshops, 2011)

A digitalized management mechanism for low-cost low-power multiple-voltage 3D designs. - Ching-Hwa Cheng; Ming-Hsuan Wu; Pin-Jui Lai; Chia-Hao Ku (DSN Workshops, 2011)

A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism. - Ching-Hwa Cheng; Jiun-In Guo (VLSI-DAT, 2012)

Integrated amorphous-Si TFT circuits for gate drivers on LCD panels. - Nan-Xiong Huang; Hsi Rong Han; Wen Tui Liao; Chih-Hung Huang; Wen Chun Wang; Miin-Shyue Shiau; Ching-Hwa Cheng; Hong-Chong Wu; Heng-Shou Hsu; Juin J. Liou; Shry-Sann Liao; Ruei-Cheng Sun; et al. (ASICON, 2013)

A low-cost scalable Voltage-Frequency Adjustor for implementing low-power systems. - Ching-Hwa Cheng; Sheng-Wei Hsu; Jiun-In Guo (ISCAS, 2013)

Reduction of current mismatching in the switches-in-source CMOS charge pump. - Miin-Shyue Shiau; Heng-Shou Hsu; Ching-Hwa Cheng; Hsiu-Hua Weng; Hong-Chong Wu; Don-Gey Liu (Microelectron. J., 2013)

Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor. - Ching-Hwa Cheng (VLSI Design, 2013)

A panoramic endoscope design and implementation for Minimally Invasive Surgery. - Chun-Hsiang Peng; Ching-Hwa Cheng (ISCAS, 2014)

An ECG front-end circuit with single power supply. - Hsiu-Cheng Lee; Jen-Bo Wang; Kai-Hsiang Juang; Kuo-Ching Hsiao; Hsung-Bie Chang; Yeng-Ting Lu; Ching-Sung Lee; Ming-Hsueh Hsiau; Qi-Ming Wan; Vu Duc Thai; Ching-Hwa Cheng; Don-Gey Liu (ICCE-TW, 2015)

A wireless panoramic endoscope system design and implementation for minimally invasive surgery. - Ching-Hwa Cheng; Sheng-Ping Hung; Jiun-In Guo; Kai-Che Liu; Jungle Chi-Hsiang Wu (ISCAS, 2015)

A power-aware quad-voltage H.264 encoder chip for wireless panoramic endoscope applications. - An-Tia Xiao; Shiang-Ren Yang; Yuan-Hsiang Miao; Ching-Hwa Cheng; Jiun-In Guo (VLSI-DAT, 2015)

SCKVdd: A Scalable Clock-Controlled Self-Stabilized Voltage Technique for Low Power CMOS Digital Circuits. - Ching-Hwa Cheng (ACM J. Emerg. Technol. Comput. Syst., 2015)

A variable-voltage low-power technique for digital circuit system. - An-Tai Xiao; Yung-Siang Miao; Ching-Hwa Cheng; Jiun-In Guo (ASP-DAC, 2016)

A hierarchy multiple-voltage design technique for low-power performance-manageable bio-chips. - Yu-Shin Wang; Ching-Hwa Cheng (ICCE-TW, 2016)

A Learnable Unmanned Smart Logistics Prototype System Design and Implementation. - I-Lok Cheng; Ching-Hwa Cheng; Don-Gey Liu (AICAS, 2019)

Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems. - Ching-Hwa Cheng; Tang-Chieh Liu (DDECS, 2019)

A Stable Video Stitching Technique for Minimally Invasive Surgery. - Dinh Thai Kim; Ching-Hwa Cheng; Don-Gey Liu (ICBET, 2019)

A Real-Time Robot-Arm Surgical Guiding System Development by Image-Tracking. - Ching-Hwa Cheng (AICAS, 2020)

A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System. - Ching-Hwa Cheng (ASP-DAC, 2020)

Development of a Portable Self-Guidance Rescue Car and a 3D-Screen LIDAR Mapping System. - Ching-Hwa Cheng; Pham Minh Dung; Tang-Chieh Liu (ISCAS, 2020)

Design and Implementation of a Pre-Surgical Investigation System by VR+AR+MR Techniques. - Ching-Hwa Cheng; Huy Anh Nguyen; Tang-Chieh Liu (ISCAS, 2020)

Low-Power 3D-PCB Stacking System Design and Validation by Automatic Voltage-Current Scalable Technique. - Ching-Hwa Cheng; Jiun-In Guo (VLSI-DAT, 2020)

An Overlapping and Leading Edge Detection Combined Technique for Distance Estimation under High-Background Lights in a Pulsed-LiDAR System. - Thanh-Tuan Nguyen; Ching-Hwa Cheng; Don-Gey Liu; Song-Toan Tran; Minh-Hai Le (IECC, 2021)

The Performance-Complexity Efficient Time-to-Digit and Data-Processing Chips Design and Validation for a LiDAR System. - Ching-Hwa Cheng; Ching-Kun Chao; Kai-Chun Yeh; Don-Gey Liu; Sheng-Di Lin (ISCAS, 2021)

An Intelligent Image-Based Force Sensing System Development to Assist Robot-Arm Surgery. - Pham Minh Dung; Ching-Hwa Cheng; Don-Gey Liu (ISCAS, 2021)

A Multiple Layer U-Net, Un-Net, for Liver and Liver Tumor Segmentation in CT. - Song-Toan Tran; Ching-Hwa Cheng; Don-Gey Liu (IEEE Access, 2021)

Live Demonstration: A Portable Four-Lenses Panoramic-Stereo Endoscope System Development. - Ching-Hwa Cheng; Don-Gey Liu (BioCAS, 2022)

A Low Power Two Lenses Wireless Panoramic Micro-Endoscopy Implemented Using Voltage-Current Adjuster and 3D-PCB Stacking Technology. - Xiang-Ren Yang; Sheng-Wei Hsu; Ching-Hwa Cheng; Don-Gey Liu (BioCAS, 2022)

Live Demonstration: A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. - Jian-Lin Zeng; Tsung-Yi Wu; Don-Gey Liu; Ching-Hwa Cheng (ISCAS, 2023)

A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. - Jian-Lin Zeng; Tsung-Yi Wu; Don-Gey Liu; Ching-Hwa Cheng (ISCAS, 2023)