A memory yield improvement scheme combining built-in self-repair and error correction codes. - Tze-Hsin Wu; Po-Yuan Chen; Mincent Lee; Bin-Yen Lin; Cheng-Wen Wu; Chen-Hung Tien; Hung-Chih Lin; Hao Chen 053; Ching-Nen Peng; Min-Jer Wang (ITC, 2012)

Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch. - Sen-Kuei Hsu; Hao Chen 053; Chung-Han Huang; Der-Jiann Liu; Wei-Hsun Lin; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (ITC, 2013)

Wafer Level Chip Scale Package copper pillar probing. - Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (ITC, 2014)

Redundancy architectures for channel-based 3D DRAM yield improvement. - Bing-Yang Lin; Wan-Ting Chiang; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (ITC, 2014)

A novel DFT architecture for 3DIC test, diagnosis and repair. - Mincent Lee; Saman Adham; Min-Jer Wang; Ching-Nen Peng; Hung-Chih Lin; Sen-Kuei Hsu; Hao Chen 053 (VLSI-DAT, 2014)

A 4-GHz universal high-frequency on-chip testing platform for IP validation. - Ping-Lin Yang; Cheng-Chung Lin; Ming-Zhang Kuo; Sang-Hoo Dhong; Chien-Min Lin; Kevin Huang 005; Ching-Nen Peng; Min-Jer Wang (VTS, 2014)

On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. - Chun-Chuan Chi; Bing-Yang Lin; Cheng-Wen Wu; Min-Jer Wang; Hung-Chih Lin; Ching-Nen Peng (IEEE Des. Test, 2014)

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. - Yu-Chieh Huang; Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (DAC, 2016)

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. - Bing-Yang Lin; Wan-Ting Chiang; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Des. Test, 2016)

A Local Parallel Search Approach for Memory Failure Pattern Identification. - Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Trans. Computers, 2016)

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. - Kai-Li Wang; Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Des. Test, 2017)

A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. - Hsuan-Hung Liu; Bing-Yang Lin; Cheng-Wen Wu; Wan-Ting Chiang; Mincent Lee; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Trans. Computers, 2017)