Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems. - Ching-Te Chiu; K. J. Ray Liu (IEEE Trans. Circuits Syst. Video Technol., 1992)

VLSI Algorithms and Architectures for Time-Recursive Discrete Sinuoidal Transforms with Applications to Real-Time Video Communications. - Ching-Te Chiu (1992)

Optimal unified IIR architectures for time-recursive discrete sinusoidal transforms. - Kuo J. Ray Liu; Ching-Te Chiu; Ravi K. Kolagotla; Joseph F. JáJá (ICASSP (3), 1993)

Unified parallel lattice structures for time-recursive discrete cosine/sine/Hartley transforms. - K. J. Ray Liu; Ching-Te Chiu (IEEE Trans. Signal Process., 1993)

Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transforms. - K. J. Ray Liu; Ching-Te Chiu; Ravi K. Kolagotla; Joseph F. JáJá (IEEE Trans. Circuits Syst. Video Technol., 1994)

Design a simple and high performance switch using a two-stage architecture. - Chih-Ying Tu; Cheng-Shang Chang; Duan-Shin Lee; Ching-Te Chiu (GLOBECOM, 2005)

A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications. - Ching-Te Chiu; Chun-Chieh Chang; Shih-Min Chen; Hou-Cheng Tzeng; Ming-Chang Du; Yu-Ho Hsu; Jen-Ming Wu; Kai-Ming Feng (IWSOC, 2005)

A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology. - Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Min-Sheng Kao; Chih-Hsien Jen; Yarsun Hsu (SoCC, 2005)

A Flexible Cross Connect LCAS for Bandwidth Maximization in 2.5G EoS. - Hou-Cheng Tzeng; Ching-Te Chiu (NCA, 2006)

A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. - Yu-Hao Hsu; Min-Sheng Kao; Hou-Cheng Tzeng; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu (ASP-DAC, 2007)

Block-Based Gradient Domain High Dynamic Range Compression Design for Real-Time Applications. - Tsun-Hsien Wang; Wei-Ming Ke; Ding-Chuang Zwao; Fang-Chu Chen; Ching-Te Chiu (ICIP (3), 2007)

Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video. - Tsun-Hsien Wang; Wei-Su Wong; Fang-Chu Chen; Ching-Te Chiu (ICIP (6), 2007)

Low Power Design of High Performance Memory Access Architecture for HDTV Decoder. - Tsun-Hsien Wang; Ching-Te Chiu (ICME, 2007)

A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. - Ching-Te Chiu; Yu-Hao Hsu; Min-Sheng Kao; Hou-Cheng Tzeng; Ming-Chang Du; Ping-Ling Yang; Ming-Hao Lu; Fanta Chen; Hung-Yu Lin; Jen-Ming Wu; Shuo-Hung Hsu; Yarsun Hsu (ISCAS, 2007)

A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications. - Chih-Hsing Lin; Ching-Te Chiu (ISCAS, 2007)

Design of ultra low power CML MUXs and latches with forward body bias. - Hsiang-Ju Hsu; Ching-Te Chiu; Yarsun Hsu (SoCC, 2007)

A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias. - Chih-Hsing Lin; Ching-Te Chiu (ICECS, 2008)

Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video. - Ching-Te Chiu; Tsun-Hsien Wang; Wei-Ming Ke; Chen-Yu Chuang; Jhih-Rong Chen; Rong Yang; Ren-Song Tsay (ICIP, 2008)

A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. - Yu-Hao Hsu; Ming-Hao Lu; Ping-Ling Yang; Fanta Chen; You-Hung Li; Min-Sheng Kao; Chih-Hsing Lin; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Yarsun Hsu (ISCAS, 2008)

A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. - Ching-Te Chiu; Tsun-Hsien Wang; Wei-Ming Ke; Chen-Yu Chuang; Jhih-Siao Huang; Wei-Su Wong; Ren-Song Tsay (SiPS, 2008)

Hardware-efficient virtual high dynamic range image reproduction. - Wei-Ming Ke; Tsun-Hsien Wang; Ching-Te Chiu (ICIP, 2009)

A 100MHz hardware-efficient boost cascaded face detection design. - Wei-Su Wong; Chih-Rung Chen; Ching-Te Chiu (ICIP, 2009)

A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology. - Min-Sheng Kao; Jen-Ming Wu; Chih-Hsing Lin; Fanta Chen; Ching-Te Chiu; Shawn S. H. Hsu (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. - Yu-Hao Hsu; Yang-Syu Lin; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Fanta Chen; Min-Sheng Kao; Yarsun Hsu (ISCAS, 2010)

Hardware-efficient image enhancement with bilateral tone adjustment. - Wei-Ming Ke; Ching-Te Chiu (ISCAS, 2010)

A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification. - Chih-Hsing Lin; Yung-Chang Chang; Wen-Chih Huang; Wei-Chih Lai; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Chun-Ming Huang; Chih-Chyau Yang; Shih-Lun Chen (ISCAS, 2010)

A novel MUX-FF circuit for low power and high speed serial link interfaces. - Wei-Yu Tsai; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Yarsun Hsu (ISCAS, 2010)

Switching Bilateral Filter With a Texture/Noise Detector for Universal Noise Removal. - Chih-Hsing Lin; Jia Shiuan Tsai; Ching-Te Chiu (IEEE Trans. Image Process., 2010)

On the design and analysis of fault tolerant NoC architecture using spare routers. - Yung-Chang Chang; Ching-Te Chiu; Shih-Yin Lin; Chung-Kai Liu (ASP-DAC, 2011)

A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. - Yu-Hao Hsu; Yang-Syu Lin; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Fanta Chen; Min-Sheng Kao; Wei-Chih Lai; Yarsun Hsu (ASP-DAC, 2011)

Handover Delay Reduction and Buffer-Based Data Recovery Scheme for Inter Multicast Broadcast Service Zone. - Sih-Kai Li; Jen-Shun Yang; Ching-Te Chiu; Po-Ting Yeh; Jenq-Neng Hwang (GLOBECOM, 2011)

Curve-based and image-based JND contrast analysis for inverse tone mapping operators. - Chih-Rung Chen; Ching-Te Chiu (ICIP, 2011)

Texture classification based low order local binary pattern for face recognition. - Ching-Te Chiu; Cyuan-Jhe Wu (ICIP, 2011)

Low visual difference virtual high dynamic range image synthesizer from a single legacy image. - Tsun-Hsien Wang; Ching-Te Chiu (ICIP, 2011)

A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit. - Fanta Chen; Min-Sheng Kao; Yu-Hao Hsu; Chih-Hsing Lin; Jen-Ming Wu; Ching-Te Chiu; Shuo-Hung Hsu (ISCAS, 2011)

Embedded transition inversion coding for low power serial link. - Wen-Chih Huang; Chih-Hsing Lin; Ching-Te Chiu (SiPS, 2011)

Saliency prediction using scene motion for JND based video compression. - Ruei-Jiun Wang; Ching-Te Chiu (SiPS, 2011)

BiTA/SWCE: Image Enhancement With Bilateral Tone Adjustment and Saliency Weighted Contrast Enhancement. - Wei-Ming Ke; Chih-Rung Chen; Ching-Te Chiu (IEEE Trans. Circuits Syst. Video Technol., 2011)

A 0.64 mm 2 Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction. - Chih-Rung Chen; Wei-Su Wong; Ching-Te Chiu (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform. - Ching-Te Chiu; Tsun-Hsien Wang; Wei-Ming Ke; Chen-Yu Chuang; Jhih-Siao Huang; Wei-Su Wong; Ren-Song Tsay; Cyuan-Jhe Wu (J. Signal Process. Syst., 2011)

A Study of NoC Topologies and Switching Arbitration Mechanisms. - Yung-Chang Chang; Ching-Te Chiu (HPCC-ICESS, 2012)

A 5.8 Gbps uniform mapping data center switch. - Wei-Chih Lai; Ching-Te Chiu (ICASSP, 2012)

Cluster-Based CAN with Enhanced Transmission Capability for Vehicle Networks. - Wei-Chiu Liu; Zhan-Yao Gu; Yarsun Hsu; Ching-Te Chiu (ICCVE, 2012)

A novel low gate-count serializer topology with Multiplexer-Flip-Flops. - Wei-Yu Tsai; Ching-Te Chiu; Jen-Ming Wu; Shawn S. H. Hsu; Yarsun Hsu; Ying-Fang Tsao (ISCAS, 2012)

A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link. - Wei-Yu Tsai; Ching-Te Chiu; Jen-Ming Wu; Shawn S. H. Hsu; Yarsun Hsu (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking. - Ching-Te Chiu; Yu-Hao Hsu; Jen-Ming Wu; Shuo-Hung Hsu; Min-Sheng Kao; Hou-Cheng Tzeng; Ming-Chang Du; Ping-Ling Yang; Ming-Hao Lu; Fanta Chen; Hung-Yu Lin; Yarsun Hsu (J. Signal Process. Syst., 2012)

Low cost illumination invariant face recognition by down-up sampling self quotient image. - Li Lin; Ching-Te Chiu (APSIPA, 2013)

Human gait analysis by body segmentation and center of gravity. - Ying-Fang Tsao; Wen-Te Liu; Ching-Te Chiu (APSIPA, 2013)

Depth-based posture recognition by radar and vision fusion for real-time applications. - I-Cheng Tsai; Ching-Te Chiu (ICASSP, 2013)

Edge curve scaling and smoothing with cubic spline interpolation. - Wei-Chen Wu; Tsun-Hsien Wang; Ching-Te Chiu (ICIP, 2013)

Edge curve scaling and smoothing with cubic spline interpolation for image upscaling. - Wei-Chen Wu; Tsun-Hsien Wang; Ching-Te Chiu (SiPS, 2013)

Embedded Transition Inversion Coding With Low Switching Activity for Serial Links. - Ching-Te Chiu; Wen-Chih Huang; Chih-Hsing Lin; Wei-Chih Lai; Ying-Fang Tsao (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology. - Ching-Te Chiu; Yu-Hao Hsu; Wei-Chih Lai; Jen-Ming Wu; Shawn S. H. Hsu; Yang-Syu Lin; Fanta Chen; Min-Sheng Kao; Yarsun Hsu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Data Center Switch for Load Balanced Fat-Trees. - Wei-Chih Lai; Ching-Te Chiu (J. Signal Process. Syst., 2013)

Gradient-based image up-scaling with local self similarity. - Loyon Kuo; Tsun-Hsien Wang; Ching-Te Chiu (GlobalSIP, 2014)

Edge-based motion and intensity prediction for video super-resolution. - Jen-Wen Wang; Ching-Te Chiu (GlobalSIP, 2014)

Boosted multi-class object detection with parallel hardware implementation for real-time applications. - Yao-Tsung Yang; Ching-Te Chiu (ICASSP, 2014)

Object recognition using bag of words with kernels for big data. - Che-Yu Wu; Ching-Te Chiu; Yarsun Hsu (ICCE-TW, 2014)

Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements. - Yung-Chang Chang; Li-Ren Huang; Hsing-Chuang Liu; Chih-Jen Yang; Ching-Te Chiu (VLSI-DAT, 2014)

A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector. - Fanta Chen; Min-Sheng Kao; Yu-Hao Hsu; Jen-Ming Wu; Ching-Te Chiu; Shawn S. H. Hsu; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Virtual HDR/LDR image synthesizer in multi-core platform. - Tsun-Hsien Wang; Jen-Wen Wang; Ching-Te Chiu (GlobalSIP, 2015)

Local binary pattern orientation based face recognition. - Yi-Kang Shen; Ching-Te Chiu (ICASSP, 2015)

Accelerating AdaBoost algorithm using GPU for multi-object recognition. - Pin Yi Tsai; Yarsun Hsu; Ching-Te Chiu; Tsai-Te Chu (ISCAS, 2015)

A real-time embedded system for human gait analysis. - Yen Wen Chien; Ching-Te Chiu; I-Zan Wu (SiPS, 2015)

Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment. - Tsun-Hsien Wang; Cheng-Wen Chiu; Wei-Chen Wu; Jen-Wen Wang; Chun-Yi Lin; Ching-Te Chiu; Jing-Jia Liou (IEEE Trans. Multim., 2015)

Editorial: Signal Processing for Communication/Biomedical Systems and Reliability Improvement. - Ching-Te Chiu; Lei Wang 003; Yin-Tsung Hwang (J. Signal Process. Syst., 2015)

Edge Curve Scaling and Smoothing with Cubic Spline Interpolation for Image Up-Scaling. - Wei-Chen Wu; Tsun-Hsien Wang; Ching-Te Chiu (J. Signal Process. Syst., 2015)

A cost-effective minutiae disk code for fingerprint recognition and its implementation. - Tsai-Te Chu; Ching-Te Chiu (ICASSP, 2016)

Fingerprint recognition with ridge features and minutiae on distortion. - Chu-Chiao Liao; Ching-Te Chiu (ICASSP, 2016)

Binary descriptor based SIFT and hardware implementation. - Che-Yu Wu; Ching-Te Chiu; Yarsun Hsu (ISCAS, 2016)

LBP edge-mapped descriptor using MGM interest points for face recognition. - Jou Lin; Ching-Te Chiu (ICASSP, 2017)

Motion clustering with hybrid-sample-based foreground segmentation for moving cameras. - Yi-Chan Wu; Ching-Te Chiu (ICASSP, 2017)

Patch-based HDR video processing for fast moving object reconstruction. - Yu-Fu Mai; Ching-Te Chiu (ICNC, 2017)

Single image super-resolution using hybrid patch search and local self-similarity. - Shen-Li Lo; Ching-Te Chiu (ISCAS, 2017)

Dry fingerprint detection for multiple image resolutions using ridge features. - Chen-Jung Wu; Ching-Te Chiu (SiPS, 2017)

Low-complexity face recognition using contour-based binary descriptor. - Jou Lin; Ching-Te Chiu (IET Image Process., 2017)

PVDC: A Binary Descriptor Using Pore-Valley Disk Code Structure for High-Resolution Partial Fingerprint Recognition. - Pei-Yin Chou; Ching-Te Chiu (ICASSP, 2018)

Resource Efficient Hardware Implementation for Real-Time Traffic Sign Recognition. - Huai-Mao Weng; Ching-Te Chiu (ICASSP, 2018)

Filter-based Deep-Compression with Global Average Pooling for Convolutional Networks. - Ting-Yun Hsiao; Yung-Chang Chang; Ching-Te Chiu (SiPS, 2018)

Video Super-resolution using Edge-based Optical Flow and Intensity Prediction. - Jen-Wen Wang; Ching-Te Chiu (J. Signal Process. Syst., 2018)

Real-time Object Detection via Pruning and a Concatenated Multi-feature Assisted Region Proposal Network. - Kuan-Hung Shih; Ching-Te Chiu; Yen-Yu Pu (ICASSP, 2019)

Multi-teacher Knowledge Distillation for Compressed Video Action Recognition on Deep Neural Networks. - Meng-Chieh Wu; Ching-Te Chiu; Kun-Hsuan Wu (ICASSP, 2019)

An Energy-Aware Bit-Serial Streaming Deep Convolutional Neural Network Accelerator. - Lien-Chih Hsu; Ching-Te Chiu; Kuan-Ting Lin (ICIP, 2019)

Filter-based deep-compression with global average pooling for convolutional networks. - Ting-Yun Hsiao; Yung-Chang Chang; Hsin-Hung Chou; Ching-Te Chiu (J. Syst. Archit., 2019)

Deep Neural Network Compression with Knowledge Distillation Using Cross-Layer Matrix, KL Divergence and Offline Ensemble. - Hsing-Hung Chou; Ching-Te Chiu; Yi-Ping Liao (APSIPA, 2020)

Fast Single-View 3D Object Reconstruction with Fine Details Through Dilated Downsample and Multi-Path Upsample Deep Neural Network. - Chia-Ho Hsu; Ching-Te Chiu; Chia-Yu Kuan (ICASSP, 2020)

Object Detection with Color and Depth Images with Multi-Reduced Region Proposal Network and Multi-Pooling. - Jiou-Ai Lin; Ching-Te Chiu; Yen-Yu Cheng (ICASSP, 2020)

Rgb-D Based Multi-Modal Deep Learning for Face Identification. - Tzu-Ying Lin; Ching-Te Chiu; Ching-Tung Tang (ICASSP, 2020)

Depth Estimation From Single Image Through Multi-Path-Multi-Rate Diverse Feature Extractor. - Wen-Yi Lo; Ching-Te Chiu; Jie-Yu Luo (ICASSP, 2020)

Fast and Accurate Embedded DCNN for Rgb-D Based Sign Language Recognition. - Ching-Chen Wang; Ching-Te Chiu; Chao-Tsung Huang; Yu-Chun Ding; Li-Wei Wang 013 (ICASSP, 2020)

Semantic Segmentation via Enhancing Context Information by Fusing Multiple High-Level Features. - Kuang-Chien Li; Ching-Te Chiu; Shan-Chien Hsiao (SiPS, 2020)

ESSA: An energy-Aware bit-Serial streaming deep convolutional neural network accelerator. - Lien-Chih Hsu; Ching-Te Chiu; Kuan-Ting Lin; Hsing-Huan Chou; Yen-Yu Pu (J. Syst. Archit., 2020)

Multi-teacher knowledge distillation for compressed video action recognition based on deep learning. - Meng-Chieh Wu; Ching-Te Chiu (J. Syst. Archit., 2020)

Real-Time Object Detection With Reduced Region Proposal Network via Multi-Feature Concatenation. - Kuan-Hung Shih; Ching-Te Chiu; Jiou-Ai Lin; Yen-Yu Bu (IEEE Trans. Neural Networks Learn. Syst., 2020)

Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy. - Yung-Chang Chang; Cihun-Siyong Alex Gong; Ching-Te Chiu (J. Signal Process. Syst., 2020)

Real-Time Edge Attention-Based Learning for Low-Light One-Stage Object Detection. - Yen-Yu Pu; Ching-Te Chiu; Shu-Yun Wu (APSIPA ASC, 2021)

3D Landmark-based Face Detection and Recognition System for Large Poses. - Ching-Tung Tang; Ching-Te Chiu; Wei-Jyun Chen (APSIPA ASC, 2021)

Efficient 2D Keypoint-based Hand Pose Estimation. - Shan-Chien Hsiao; Ching-Te Chiu (CSCI, 2021)

High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator. - Kuan-Ting Lin; Ching-Te Chiu; Jheng-Yi Chang; Shan-Chien Hsiao (ISCAS, 2021)

Real-Time Block-Based Embedded CNN for Gesture Classification on an FPGA. - Ching-Chen Wang; Yu-Chun Ding; Ching-Te Chiu; Chao-Tsung Huang; Yen-Yu Cheng; Shih-Yi Sun; Chih-Han Cheng; Hsueh-Kai Kuo (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Object Detection in RGB-D Images via Anchor Box with Multi-Reduced Region Proposal Network and Multi-Pooling. - Jiou-Ai Lin; Ching-Te Chiu; Yen-Yu Cheng (J. Signal Process. Syst., 2021)

Lightweight and Efficient Neural Network Using Progressively Greedy Search. - Jheng-Yi Chang; Ching-Te Chiu; Pin-Hsuan Chen (AICAS, 2022)

RGBD-based Hardware Friendly Head Pose Estimation System via Convolutional attention module. - Yen-Yu Cheng; Ching-Te Chiu; Yi-Fan Chen (ISCAS, 2022)

Multi-View RGB-D Based 3D Point Cloud Face Model Reconstruction System. - Jie-Yu Luo; Ching-Te Chiu; An-Ting Hsieh (ISCAS, 2022)

Chaos LiDAR Based RGB-D Face Classification System With Embedded CNN Accelerator on FPGAs. - Ching-Te Chiu; Yu-Chun Ding; Wei-Chen Lin; Wei-Jyun Chen; Shu-Yun Wu; Chao-Tsung Huang; Chun-Yeh Lin; Chia-Yu Chang; Meng-Jui Lee; Shimazu Tatsunori; Tsung Chen; Fan-Yi Lin; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Landmark-Based Adversarial Network for RGB-D Pose Invariant Face Recognition. - Wei-Jyun Chen; Ching-Te Chiu; Ting-Chun Lin (AICAS, 2023)

CPGAN: Collective Punishment Generative Adversarial Network for Dry Fingerprint Image Enhancement. - Yu-Chi Su; Ching-Te Chiu; Chih-Han Cheng; Kuan-Hsien Liu; Tsung-Chan Lee; Jia-Lin Chen; Jie-Yu Luo; Wei-Chang Chung; Yao-Ren Chang; Kuan-Ying Ho (AICAS, 2023)

Machine Learning Based Action Recognition with Modular CNN. - Shi-Zong Huang; Ching-Te Chiu; Yu-Jen Chang (APSIPA ASC, 2023)

RGB-D Based Pose-Invariant Face Recognition Via Attention Decomposition Module. - Wei-Chen Lin; Ching-Te Chiu; Kuan-Chang Shih (ICASSP, 2023)

Low Temperature and Dry Fingerprint Restoration with Ridge Loss and Orientation. - Hsueh-Kai Kuo; Ching-Te Chiu; Lien-Chieh Huang (NEWCAS, 2023)

Pose Aware RGBD-based Face Recognition System With Hierarchical Bilinear Pooling. - Shu-Yun Wu; Ching-Te Chiu; Yung-Ching Hsu (NEWCAS, 2023)

Multiple Training Stage Image Enhancement Enrolled With CCRGAN Pseudo Templates for Large Area Dry Fingerprint Recognition. - Chih-Han Cheng; Ching-Te Chiu; Chia-Yu Kuan; Yu-Chi Su; Kuan-Hsien Liu; Tsung-Chan Lee; Jia-Lin Chen; Jie-Yu Luo; Wei-Chang Chung; Yao-Ren Chang; Kuan-Ying Ho (IEEE Access, 2023)

PGT-Net: Progressive Guided Multi-task Neural Network for Small-area Wet Fingerprint Denoising and Recognition. - Yu-Ting Li; Ching-Te Chiu; An-Ting Hsieh; Mao-Hsiu Hsu; Wenyong Long; Jui-Min Hsu (CoRR, 2023)

EfficientNet-eLite: Extremely Lightweight and Efficient CNN Models for Edge Devices by Network Candidate Search. - Ching-Chen Wang; Ching-Te Chiu; Jheng-Yi Chang (J. Signal Process. Syst., 2023)

Multi-Layer Relation Knowledge Distillation For Fingerprint Restoration. - Yu-Min Chiu; Ching-Te Chiu; Dao-Heng Luo (ICASSP, 2024)

Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction. - Yi-Fan Chen; Yu-Jen Chang; Ching-Te Chiu; Ming-Long Huang; Geng-Ming Liang; Chao-Lin Lee; Jenq-Kuen Lee; Ping-Yu Hsieh; Wei-Chih Lai (ISCAS, 2024)

Feature Points based Residual UNet with Nonlinear Decay Rate for Partial Wet Fingerprint Restoration and Recognition. - An-Ting Hsieh; Ching-Te Chiu; Tsai-Chieh Chen; Mao-Hsiu Hsu; Wenyong Long (ISCAS, 2024)

High Utilization Vision Transformer Accelerator with Flexible Dataflow. - Ting-Chun Lin; Ching-Te Chiu; Jhao-Wei Chen (NewCAS, 2025)

Inpainting Diffusion Synthetic and Data Augment With Feature Keypoints for Tiny Partial Fingerprints. - Mao-Hsiu Hsu; Yung-Ching Hsu; Ching-Te Chiu (IEEE Trans. Biom. Behav. Identity Sci., 2025)