Failure Factor Based Yield Enhancement for SRAM Designs. - Yu-Tsao Hsing; Chih-Wea Wang; Ching-Wei Wu; Chih-Tsun Huang; Cheng-Wen Wu (DFT, 2004)

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS. - Ching-Wei Wu; Ming-Hung Chang; Chia-Cheng Chen; Robin Lee; Hung-Jen Liao; Jonathan Chang (A-SSCC, 2014)

Study of Scraping guide Ways Inspection. - Ching-Wei Wu; Ying-Shing Shiao; Ching-Feng Chang (J. Comput., 2014)

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications. - Yen-Huei Chen; Kao-Cheng Lin; Ching-Wei Wu; Wei-Min Chan; Jhon-Jhy Liaw; Hung-Jen Liao; Jonathan Chang (VLSI Circuits, 2016)

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications. - Michael Clinton; Hank Cheng; Hung-Jen Liao; Robin Lee; Ching-Wei Wu; Johnny Yang; Hau-Tai Hsieh; Frank Wu; Jung-Ping Yang; Atul Katoch; Arun Achyuthan; Donald Mikan; et al. (ISSCC, 2017)

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Sevic Chen; Peijiun Lin; Ching-Wei Wu; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; et al. (VLSI Technology and Circuits, 2023)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)