On rewiring and simplification for canonicity in threshold logic circuits. - Pin-Yi Kuo; Chun-Yao Wang; Ching-Yi Huang (ICCAD, 2011)

A register-transfer level testability analyzer. - Yen-An Chen; Chun-Yao Wang; Ching-Yi Huang; Hsiu-Yi Lin (SoCC, 2011)

A probabilistic analysis method for functional qualification under Mutation Analysis. - Hsiu-Yi Lin; Chun-Yao Wang; Shih-Chieh Chang; Yung-Chih Chen; Hsuan-Ming Chou; Ching-Yi Huang; Yen-Chi Yang; Chun-Chien Shen (DATE, 2012)

Using "Learning Video Portfolio" to Enhance Students' Metacognition in Authentic Learning. - Ching-Yi Huang; Chi-Wen Huang; Chia-Jung Wu; Gwo-Dong Chen; Kuang-Hung Chiang (ICALT, 2012)

Using Kinect to Track Learning Behavior of Students in the Classroom as Video Portfolio to Enhance Reflection Learning. - Chuan-Ling Lien; Ching-Yi Huang; Chin-Yeh Wang; Gwo-Dong Chen (ICCE, 2012)

Error Injection & Correction: An efficient formal logic restructuring algorithm. - Ching-Yi Huang; Daw-Ming Lee; Chun-Chi Lin; Chun-Yao Wang (ISOCC, 2012)

On reconfigurable single-electron transistor arrays synthesis using reordering techniques. - Chang-En Chiang; Li-Fu Tang; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (DATE, 2013)

Sensitization criterion for threshold logic circuits and its application. - Chen-Kuan Tsai; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen (ICCAD, 2013)

Pattern generation for Mutation Analysis using Genetic Algorithms. - Yen-Chi Yang; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen (ISCAS, 2013)

Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays. - Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Rewiring for threshold logic circuit minimization. - Chia-Chun Lin; Chun-Yao Wang; Yung-Chih Chen; Ching-Yi Huang (DATE, 2014)

Width minimization in the Single-Electron Transistor array synthesis. - Chian-Wei Liu; Chang-En Chiang; Ching-Yi Huang; Chun-Yao Wang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (DATE, 2014)

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. - Ching-Yi Huang; Chian-Wei Liu; Chun-Yao Wang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (ASP-DAC, 2015)

Using structural relations for checking combinationality of cyclic circuits. - Wan-Chen Weng; Yung-Chih Chen; Jui-Hung Chen; Ching-Yi Huang; Chun-Yao Wang (DATE, 2015)

Synthesis and verification of cyclic combinational circuits. - Jui-Hung Chen; Yung-Chih Chen; Wan-Chen Weng; Ching-Yi Huang; Chun-Yao Wang (SoCC, 2015)

Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits. - Ching-Yi Huang; Zheng-Shan Yu; Yung-Chun Hu; Tung-Chen Tsou; Chun-Yao Wang; Yung-Chih Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Synthesis for Width Minimization in the Single-Electron Transistor Array. - Chian-Wei Liu; Chang-En Chiang; Ching-Yi Huang; Yung-Chih Chen; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2015)

MajorSat: A SAT solver to majority logic. - Yu-Min Chou; Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang (ASP-DAC, 2016)

An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm. - Tai-Lin Chen; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen (J. Multiple Valued Log. Soft Comput., 2016)

Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks. - Chen-Yu Lin; Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang; Chiou-Ting Hsu (IEEE Trans. Multi Scale Comput. Syst., 2016)

Area-Aware Decomposition for Single-Electron Transistor Arrays. - Ching-Hsuan Ho; Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang; Suman Datta; Vijaykrishnan Narayanan (ACM Trans. Design Autom. Electr. Syst., 2016)

Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. - Ching-Yi Huang; Yun-Jui Li; Chian-Wei Liu; Chun-Yao Wang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

ICCAD-2017 CAD contest in resource-aware patch generation. - Ching-Yi Huang; Chih-Jen Hsu; Chi-An Wu; Kei-Yong Khoo (ICCAD, 2017)

Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. - Yun-Jui Li; Ching-Yi Huang; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Using range-equivalent circuits for facilitating bounded sequential equivalence checking. - Yung-Chih Chen; Wei-An Ji; Chih-Chung Wang; Ching-Yi Huang; Chia-Cheng Wu; Chia-Chun Lin; Chun-Yao Wang (VLSI-DAT, 2018)

2019 CAD Contest: Logic Regression on High Dimensional Boolean Space. - Ching-Yi Huang; Chi-An (Rocky) Wu; Tung-Yuan Lee; Chih-Jen (Jacky) Hsu; Kei-Yong Khoo (ICCAD, 2019)

ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk. - Chih-Jen Hsu; Chi-An Wu; Ching-Yi Huang; Kei-Yong Khoo (ICCAD, 2020)