New dynamic flip-flops for high-speed dual-modulus prescaler. - Ching-Yuan Yang; Guang-Kaai Dehng; June-Ming Hsu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 1998)

Clock-deskew buffer using a SAR-controlled delay-locked loop. - Guang-Kaai Dehng; June-Ming Hsu; Ching-Yuan Yang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2000)

A 900-MHz 1-V CMOS frequency synthesizer. - Guang-Kaai Dehng; Ching-Yuan Yang; June-Ming Hsu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2000)

Fast-switching frequency synthesizer with a discriminator-aided phase detector. - Ching-Yuan Yang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2000)

A one-wire approach for skew-compensating clock distribution based on bidirectional techniques. - Ching-Yuan Yang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2001)

A wide-range delay-locked loop with a fixed latency of one clock cycle. - Hsiang-Hui Chang; Jyh-Woei Lin; Ching-Yuan Yang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2002)

A high-frequency phase-compensation fractional-N frequency synthesizer. - Ching-Yuan Yang; Jen-Wen Chen; Meng-Ting Tsai (ISCAS (5), 2005)

A 0.18-µm CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniques. - Ching-Yuan Yang; Yu Lee (ISCAS (2), 2005)

A 6.5-GHz LC VCO with Integrated-Transformer Tuning. - Chia-Chieh Tu; Ching-Yuan Yang (APCCAS, 2006)

A 3.125-GHz Limiting Amplifier for Optical Receiver System. - Hsin-Ming Wu; Ching-Yuan Yang (APCCAS, 2006)

A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels. - Meng-Ting Tsai; Ching-Yuan Yang (ISCAS, 2006)

A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique. - Jun-Hong Weng; Meng-Ting Tsai; Jung-Mao Lin; Ching-Yuan Yang (ISCAS, 2006)

A low-noise microsensor amplifier with automatic gain control system. - Jun-Hong Weng; Chong-Jng Yu; Ching-Yuan Yang; Peng-Chang Yang (ISCAS, 2006)

A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector. - Ching-Yuan Yang; Yu Lee; Cheng-Hsing Lee (IEICE Trans. Electron., 2006)

High-Frequency Low-Noise Voltage-Controlled LC-Tank Oscillators Using a Tunable Inductor Technique. - Ching-Yuan Yang; Meng-Ting Tsai (IEICE Trans. Electron., 2006)

A Fast-Locking Agile Frequency Synthesizer for MIMO Dual-mode WiFi / WiMAX Applications. - Meng-Ting Tsai; Ching-Yuan Yang (ICECS, 2007)

A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation. - Ching-Yuan Yang; Jung-Mao Lin (IEICE Trans. Electron., 2007)

A programmable duty cycle corrector based on delta-sigma modulated PWM mechanism. - Gung-Yu Lin; Ching-Yuan Yang; Yu Lee; Jun-Hong Weng (APCCAS, 2008)

A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique. - Kai Pong Wu; Ching-Yuan Yang; Jung-Mao Lin (APCCAS, 2008)

Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications. - Ching-Yuan Yang; Ken-Hao Chang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology. - Ching-Yuan Yang; Chih-Hsiang Chang; Wen-Ger Wong (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Acoustic-Resonance-Free High-Frequency Electronic Ballast for Metal Halide Lamps. - Chin-Sien Moo; Chun-Kai Huang; Ching-Yuan Yang (IEEE Trans. Ind. Electron., 2008)

A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers. - Ching-Yuan Yang; Yu Lee (IEEE Trans. Instrum. Meas., 2008)

A Delta-Sigma PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology. - Ching-Yuan Yang; Chih-Hsiang Chang; Wen-Ger Wong (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

An embedded wide-range and high-resolution CLOCK jitter measurement circuit. - Yu Lee; Ching-Yuan Yang; Nai-Chen Daniel Cheng; Ji-Jan Chen (DATE, 2010)

A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique. - Jun-Hong Weng; Ching-Yuan Yang; Yi-Lin Jhu (ISLPED, 2011)

A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35- μ m SiGe BiCMOS. - Ching-Yuan Yang; Jun-Hong Weng; Hsuan-Yu Chang (IEEE J. Solid State Circuits, 2011)

A 0.5/0.8-V 9-GHz Frequency Synthesizer With Doubling Generation in 0.13-μm CMOS. - Ching-Yuan Yang; Chih-Hsiang Chang; Jun-Hong Weng; Hsin-Ming Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A chip-to-chip clock-deskewing circuit for 3-D ICs. - Ai-Jia Chuang; Yu Lee; Ching-Yuan Yang (ISCAS, 2012)

A 22-GHz low-power frequency synthesizer in 0.18-um CMOS. - Ching-Yuan Yang; Jia-Jiun Lin; Chih-Hsiang Chang (ISCIT, 2012)

A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS. - Chih-Hsiang Chang; Ching-Yuan Yang; Yu Lee; Jun-Hong Weng; Nai-Chen Cheng 001 (ESSCIRC, 2013)

A high-speed low-power calibrated flash ADC. - Hsuan-Yu Chang; Ching-Yuan Yang (ISCAS, 2014)

A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment. - Jung-Mao Lin; Ching-Yuan Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling. - Jung-Mao Lin; Ching-Yuan Yang; Hsin-Ming Wu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication Systems. - Po-Tsang Chen; Ching-Yuan Yang (ISVLSI, 2016)

A Reference Voltage Interpolation-Based Calibration Method for Flash ADCs. - Hsuan-Yu Chang; Ching-Yuan Yang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 1.5-Gb/s equalizer with adaptive swing controller for TFT-LCD driver. - Yen-Chen Lin; Ching-Yuan Yang; James Chang (ISOCC, 2017)

A 1.5-Gb/s adaptive equalizer with periodically embedded clock encoding for intra-panel interfaces. - Chia-Chi Liu; Ching-Yuan Yang (ISOCC, 2017)

W2A: Analog-to-digital converters and low-noise amplifiers. - Ching-Yuan Yang (SoCC, 2017)

Realization of buck converter with adaptive variable-frequency control. - Ching-Yuan Yang; Jen-Yan Huang; Jun-Hong Weng (SoCC, 2017)

Cascading Convolutional Neural Network for Steel Surface Defect Detection. - Chih-Yang Lin; Cheng-Hsun Chen; Ching-Yuan Yang; Fityanul Akhyar; Chao-Yung Hsu; Hui-Fuang Ng (AHFE (14), 2019)

PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems. - Miao-Shan Li; Yen-Kuei Lu; Ching-Yuan Yang; Chin-Lung Lin (ISOCC, 2019)

Flipping Rectifiers for Piezoelectric Vibration Energy Harvesting. - Wan-Ling Wu; Yong-Zheng Wang; Ching-Yuan Yang (ISOCC, 2019)

A Spur-Suppression Technique for Frequency Synthesizer with Pulse-Width to Current Conversion. - Po-Yu Hsieh; Shao-Yu Shu; Ching-Yuan Yang (ISPACS, 2019)

A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL. - You-Sheng Lin; Miao-Shan Li; Ching-Yuan Yang (SoCC, 2019)

A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection. - Guan-Min Luo; Ching-Yuan Yang (SoCC, 2019)

A Flipping Active-Diode Rectifier for Piezoelectric-Vibration Energy-Harvesting. - Wan-Ling Wu; Ching-Yuan Yang; Dung-An Wang (ECCTD, 2020)

A High-Efficiency Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting. - Hao-Hsiang Hsu; Ching-Yuan Yang; Dung-An Wang (ISOCC, 2020)

A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth. - Yen-Kuei Lu; Miao-Shan Li; Ching-Yuan Yang; Chin-Lung Lin (A-SSCC, 2021)

A Self Synchronized-Switch Rectifier for Piezoelectric-Vibration Energy-Harvesting Systems. - Yong-Zheng Wang; Ching-Yuan Yang (ISOCC, 2021)

A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links. - Ching-Yuan Yang; Miao-Shan Li; Ai-Jia Chuang (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 80-MHz 91.2 ppm/°C Self-Biased Frequency-Locked-Loop Timer. - Tsung-Ying Chen; Ching-Yuan Yang; Dung-An Wang (ISOCC, 2022)

A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion. - Shao-Yu Shu; Chun-Hung Lin; Ching-Yuan Yang (VLSI-DAT, 2022)

Behavior Simulation of CDR for SSC System With a Compact Quarter-Rate Linear Phase Detector. - Shu-Chi Wang; Ching-Yuan Yang (ISOCC, 2023)

Behavior Simulation of SSC Generator With Adjustable Modulation Frequency and Depth. - Wan-Yu You; Ching-Yuan Yang (ISOCC, 2023)

A 30-GHz Frequency Doubler Using a Current Folding Technique in 90-nm CMOS Technology. - Ke-Chiao Chou; Chun-Hung Lin; Ching-Yuan Yang (MOCAST, 2023)