A probabilistic multicommodity-flow solution to circuit clustering problems. - Ching-Wei Yeh; Chung-Kuan Cheng; Ting-Ting Y. Lin (ICCAD, 1992)

A general purpose, multiple-way partitioning algorithm. - Ching-Wei Yeh; Chung-Kuan Cheng; Ting-Ting Y. Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Block-oriented programmable design with switching network interconnect. - Chingwei Yeh; Lung-Tien Liu; Chung-Kuan Cheng; T. C. Hu; S. Ahmed; M. Liddel (IEEE Trans. Very Large Scale Integr. Syst., 1994)

On the acceleration of flow-oriented circuit clustering. - Ching-Wei Yeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Optimization by iterative improvement: an experimental evaluation on two-way partitioning. - Ching-Wei Yeh; Chung-Kuan Cheng; Ting-Ting Y. Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Circuit clustering using a stochastic flow injection method. - Ching-Wei Yeh; Chung-Kuan Cheng; Ting-Ting Y. Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

On the integration of partitioning and global routing for rectilinear placement problems. - Chingwei Yeh; Chi-Shong Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs. - Ching-Wei Yeh; Min-Cheng Chang; Yin-Shuin Kang (ARVLSI, 1999)

Technnology Mapping for Low Power. - Ching-Wei Yeh; Chin-Chao Chang; Jinn-Shyan Wang (ASP-DAC, 1999)

Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. - Ching-Wei Yeh; Min-Cheng Chang; Shih-Chieh Chang; Wen-Ben Jone (DAC, 1999)

Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. - Ching-Wei Yeh; Yin-Shuin Kang; Shan-Jih Shieh; Jinn-Shyan Wang (DAC, 1999)

Power reduction through iterative gate sizing and voltage scaling. - Chingwei Yeh; Min-Cheng Chang; Shih-Chieh Chang; Wen-Ben Jone (ISCAS (1), 1999)

A cell selection strategy for low power applications. - Chingwei Yeh; Chin-Chao Chang; Jinn-Shyan Wang (ISCAS (6), 1999)

A simulated annealing based method supporting dual supply voltages in standard cell placement. - Chingwei Yeh; Yin-Shuin Kang (ISCAS (1), 1999)

Cell-based layout techniques supporting gate-level voltage scaling for low power. - Chingwei Yeh; Yin-Shuin Kang (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Analysis and design of high-speed and low-power CMOS PLAs. - Jinn-Shyan Wang; Ching-Rong Chang; Chingwei Yeh (IEEE J. Solid State Circuits, 2001)

An adaptive path selection method for delay testing. - Wen-Ben Jone; Wu-Sung Yeh; Chingwei Yeh; Sunil R. Das (IEEE Trans. Instrum. Meas., 2001)

A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. - Kuan-Hung Chen; Jiun-In Guo; Jinn-Shyan Wang; Ching-Wei Yeh (ICME, 2004)

A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. - Kuan-Hung Chen; Jiun-In Guo; Jinn-Shyan Wang; Ching-Wei Yeh; Tien-Fu Chen (ISCAS (2), 2004)

Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. - Jinn-Shyan Wang; Shang-Jyh Shieh; Ching-Wei Yeh; Yuan-Hsun Yeh (ISCAS (2), 2004)

The CMOS carry-forward adders. - Chung-Hsun Huang; Jinn-Shyan Wang; Chingwei Yeh; Chih-Jen Fang (IEEE J. Solid State Circuits, 2004)

A low-power high-SFDR CMOS direct digital frequency synthesizer. - Jinn-Shyan Wang; Shiang-Jiun Lin; Chingwei Yeh (ISCAS (2), 2005)

Design techniques for single-low-VDD CMOS systems. - Jinn-Shyan Wang; Hung-Yu Li; Chingwei Yeh; Tien-Fu Chen (IEEE J. Solid State Circuits, 2005)

An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. - Kuan-Hung Chen; Jiun-In Guo; Jinn-Shyan Wang; Ching-Wei Yeh; Jia-Wei Chen (IEEE Trans. Circuits Syst. Video Technol., 2005)

Timing driven power gating. - De-Shiuan Chiou; Shih-Hsin Chen; Shih-Chieh Chang; Chingwei Yeh (DAC, 2006)

An 830mW, 586kbps 1024-bit RSA chip design. - Chingwei Yeh; En-Feng Hsu; Kai-Wen Cheng; Jinn-Shyan Wang; Nai-Jen Chang (DATE Designers' Forum, 2006)

A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. - Chingwei Yeh; Chao-Ching Wang; Lin-Chi Lee; Jinn-Shyan Wang (DATE Designers' Forum, 2006)

Design of STR level converters for SoCs using the multi-island dual-VDD design technique. - Jinn-Shyan Wang; Yu-Juey Chang; Chingwei Yeh; Yuan-Hua Chu (ISCAS, 2006)

TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines. - Jinn-Shyan Wang; Chao-Ching Wang; Chingwei Yeh (ISSCC, 2006)

An AND-type match-line scheme for high-performance energy-efficient content addressable memories. - Hung-Yu Li; Chia-Cheng Chen; Jinn-Shyan Wang; Chingwei Yeh (IEEE J. Solid State Circuits, 2006)

Performance-driven technology mapping with MSG partition and selective gate duplication. - Chi-Shong Wang; Chingwei Yeh (ACM Trans. Design Autom. Electr. Syst., 2006)

Power minimization for dynamic PLAs. - Tzyy-Kuen Tien; Chih-Shen Tsai; Shih-Chieh Chang; Chingwei Yeh (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. - Chang-Ching Yeh; Kuei-Chung Chang; Tien-Fu Chen; Chingwei Yeh (HiPEAC, 2007)

A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS. - Jinn-Shyan Wang; Jian-Shiun Chen; Yi-Ming Wang; Chingwei Yeh (ISSCC, 2007)

High-Speed and Low-Power Design Techniques for TCAM Macros. - Chao-Ching Wang; Jinn-Shyan Wang; Chingwei Yeh (IEEE J. Solid State Circuits, 2008)

Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays. - Jinn-Shyan Wang; Yu-Juey Chang; Chingwei Yeh (IEICE Trans. Electron., 2010)

Adaptive Pipeline voltage Scaling in High Performance Microprocessor. - Chang-Ching Yeh; Kuei-Chung Chang; Tien-Fu Chen; Chingwei Yeh (J. Circuits Syst. Comput., 2010)

Low power shift registers for megabits CMOS image sensors. - Jinn-Shyan Wang; Tsung-Han Hsieh; Keng-Jui Chang; Chingwei Yeh (ASICON, 2011)

Variation-resilient voltage generation for SRAM weak cell testing. - Chingwei Yeh; Yan-Nan Liu; Jinn-Shyan Wang; Pei-Yao Chang (ASICON, 2011)

RSCE-aware ultra-low-voltage 40-nm CMOS circuits. - Jinn-Shyan Wang; Keng-Jui Chang; Shu-Yi Yang; Tsung-Han Hsieh; Chingwei Yeh (ISOCC, 2011)

Design of High-Performance CMOS Level Converters Considering PVT Variations. - Jinn-Shyan Wang; Yu-Juey Chang; Chingwei Yeh (IEICE Trans. Electron., 2011)

Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy. - Chang-Ching Yeh; Kuei-Chung Chang; Tien-Fu Chen; Chingwei Yeh (ACM Trans. Archit. Code Optim., 2011)

Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications. - Shyang-Chyun Chen; Chao-Chuan Chen; Wen-Chi Guo; Tay-Jyi Lin; Ching-Wei Yeh (ASP-DAC, 2012)

Towards Process Variation-Aware Power Gating. - Chingwei Yeh; Yuan-Chang Chen; Jinn-Shyan Wang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS. - Jian-Shiun Chen; Chingwei Yeh; Jinn-Shyan Wang (ISSCC, 2013)

Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. - Jinn-Shyan Wang; Keng-Jui Chang; Chingwei Yeh; Shih-Chieh Chang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Maintaining color fidelity for dual-shot HDR imaging. - Chingwei Yeh; Chen-Yao Tsai; Tay-Jyi Lin; Jiun-In Guo (ICCE-TW, 2014)

A low complexity edge-preserved image compression algorithm for LCD overdrive. - Chao-Yang Chang; Chung-Hsun Huang; Hui-Fu Chen; Chingwei Yeh; Yuan-Sun Chu; Tay-Jyi Lin (GCCE, 2016)

Variable-length VLIW encoding for code size reduction in embedded processors. - Ting-Yu Shyu; Bo-Yu Su; Tay-Jyi Lin; Chingwei Yeh; Jinn-Shyan Wang; Tien-Fu Chen (SoCC, 2016)

Approximate Distributed Arithmetic for Variable-Latency Table Lookup. - Yi-Hsuan Ting; Tay-Jyi Lin; Cheng-Chun Chang; Chih-Chien Hu; Chingwei Yeh; Jinn-Shyan Wang (NGCAS, 2017)

A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. - Tay-Jyi Lin; Chen-Zong Liao; You-Jia Hu; Wei-Cheng Hsu; Zheng-Xian Wu; Shao-Yu Wang; Chun-Ming Huang; Ying-Hui Lai; Chingwei Yeh; Jinn-Shyan Wang (ASP-DAC, 2022)

Force-Sensing Intelligent Vise for Cutting Dynamics Monitoring in Machining. - Po-Han Chen; Tay-Jyi Lin; Chingwei Yeh; Pei-Zen Chang; Wei-Chang Li (SENSORS, 2023)

A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. - Tay-Jyi Lin; Yi-Hsuan Ting; Meng-Ze Hsu; Kuan-Han Lin; Chung-Ming Huang; Fu-Cheng Tsai; Shyh-Shyuan Sheu; Shih-Chieh Chang; Chingwei Yeh; Jinn-Shyan Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Performance Evaluation of MEMS Vibration Sensors for Throat Microphones. - Che-Yu Hsu; Po-Han Chen; Ting-Yi Chen; Shang-Yu Lin; Ching-Jen Wang; Chingwei Yeh; Tay-Jyi Lin; Pei-Zen Chang; Wei-Chang Li (IEEE SENSORS, 2024)