New bit-parallel systolic multipliers for a class of GF(2m). - Chiou-Yng Lee; Erl-Huei Lu; Jau-Yien Lee (ISCAS (4), 2001)

Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials. - Chiou-Yng Lee; Erl-Huei Lu; Jau-Yien Lee (IEEE Trans. Computers, 2001)

Low-complexity systolic multiplier over GF(2m) using weakly dual basis. - Chiou-Yng Lee; Ya-Cheng Lu; Erl-Huei Lu (APCCAS (1), 2002)

Low-Latency Bit-Parallel Systolic Multiplier for Irreducible xm + xn + 1 with GCD(m, n) = 1. - Chiou-Yng Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Low-complexity linear array multiplier for normal basis of type-II. - Chiou-Yng Lee; Chung-Jyi Chang (ICME, 2004)

Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm. - Chiou-Yng Lee; Che Wun Chiou; Jim-Min Lin (Comput. Electr. Eng., 2005)

Multiplexer-based double-exponentiation for normal basis of GF(2m). - Che Wun Chiou; Chiou-Yng Lee (Comput. Secur., 2005)

Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m). - Chiou-Yng Lee; Che Wun Chiou; Jim-Min Lin (J. Electron. Test., 2005)

Efficient Design of Low-Complexity Bit-Parallel Systolic Hankel Multipliers to Implement Multiplication in Normal and Dual Bases of GF (2m). - Chiou-Yng Lee; Che Wun Chiou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m). - Chiou-Yng Lee; Jenn-Shyong Horng; I-Chang Jou; Erl-Huei Lu (IEEE Trans. Computers, 2005)

New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm. - Chiou-Yng Lee; Yu-Hsin Chiu; Che Wun Chiou (APCCAS, 2006)

Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m). - Chiou-Yng Lee; Chin-Chin Chen; Yuan-Ho Chen; Erl-Huei Lu (SMC, 2006)

Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m). - Chiou-Yng Lee; Che Wun Chiou; Jim-Min Lin (J. Electron. Test., 2006)

Concurrent Error Detection in Montgomery Multiplication over GF(2m). - Che Wun Chiou; Chiou-Yng Lee; An-Wen Deng; Jim-Min Lin (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation. - Chiou-Yng Lee; Jenn-Shyong Horng; I-Chang Jou (J. Comput. Sci. Technol., 2006)

Low-Complexity Parallel Systolic Architectures for Computing Multiplication and Squaring over FG(2m). - Chiou-Yng Lee; Yung-Hui Chen (AINA Workshops (1), 2007)

Scalable and systolic Montgomery multiplier over GF(2m) generated by trinomials. - Chiou-Yng Lee; Che Wun Chiou; Jim-Min Lin; Chin-Chen Chang 001 (IET Circuits Devices Syst., 2007)

Unified Parallel Systolic Multiplier Over GF(2m). - Chiou-Yng Lee; Yung-Hui Chen; Che Wun Chiou; Jim-Min Lin (J. Comput. Sci. Technol., 2007)

Concurrent Error Detection in Digit-Serial Normal Basis Multiplication over GF(2m). - Chiou-Yng Lee (AINA Workshops, 2008)

Efficient Bit-Parallel Multipliers in Composite Fields. - Chiou-Yng Lee; Pramod Kumar Meher (APSCC, 2008)

Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2m). - Chin-Chin Chen; Chiou-Yng Lee; Erl-Huei Lu (Mobility Conference, 2008)

Multiplexer-based bit-parallel systolic multipliers over GF(2m). - Chiou-Yng Lee (Comput. Electr. Eng., 2008)

Scalable and Systolic Montgomery Multipliers over GF(2m). - Chin-Chin Chen; Chiou-Yng Lee; Erl-Huei Lu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Low-Complexity Parallel Systolic Montgomery Multipliers over GF(2m) Using Toeplitz Matrix-Vector Representation. - Chiou-Yng Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Low-complexity bit-parallel systolic multipliers over GF(2m). - Chiou-Yng Lee (Integr., 2008)

New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations. - Chiou-Yng Lee; Che Wun Chiou (J. Signal Process. Syst., 2008)

An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. - Pramod Kumar Meher; Yajun Ha; Chiou-Yng Lee (ASP-DAC, 2009)

Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition. - Pramod Kumar Meher; Chiou-Yng Lee (ISCAS, 2009)

Implementation of an interactive mobile robot over mixed reality. - Wen-Yo Lee; Jhu-Syuan Guo; Chiou-Yng Lee; Chan-An Pao; Ta-Chih Hung (ROBIO, 2009)

Concurrent error detection and correction in dual basis multiplier over GF(2m). - Che Wun Chiou; Chiou-Yng Lee; Jim-Min Lin; Ting-Wei Hou; Chin-Chen Chang 001 (IET Circuits Devices Syst., 2009)

Unified dual-field multiplier in GF(P) and GF(2k). - Che Wun Chiou; Chiou-Yng Lee; Jim-Min Lin (IET Inf. Secur., 2009)

Concurrent Error Detection and Correction in Gaussian Normal Basis Multiplier over GF(2^m). - Che Wun Chiou; Chin-Chen Chang 001; Chiou-Yng Lee; Ting-Wei Hou; Jim-Min Lin (IEEE Trans. Computers, 2009)

Concurrent Error Detection in Shifted Dual Basis Multiplier over GF(2m) Using Cyclic Code Approach. - Chiou-Yng Lee; Yu-Hsin Chiu; Jung-Hui Chiu (AINA Workshops, 2010)

Fast Optimal Normal Basis Multiplier with Type-2kw Over GF (2m). - Che Wun Chiou; Jim-Min Lin; Chiou-Yng Lee (CASoN, 2010)

Concurrent Error Detection in Systolic Array AB^2 Multiplier Using Linear Codes. - Chiou-Yng Lee (CASoN, 2010)

Error-Correcting Codes for Concurrent Error Correction in Bit-Parallel Systolic and Scalable Multipliers for Shifted Dual Basis of GF(2m). - Chiou-Yng Lee (ISPA, 2010)

Efficient bit-parallel multipliers over finite fields GF(2m). - Chiou-Yng Lee; Pramod Kumar Meher (Comput. Electr. Eng., 2010)

Concurrent error detection in semi-systolic dual basis multiplier over GF(2m) using self-checking alternating logic. - Che Wun Chiou; Wen-Yew Liang; Hung Wei Chang; Jim-Min Lin; Chiou-Yng Lee (IET Circuits Devices Syst., 2010)

Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m). - Chiou-Yng Lee (Integr., 2010)

Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction Schemes. - Chiou-Yng Lee; Pramod Kumar Meher; Jagdish Chandra Patra (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2m) Using Double Parity Prediction Scheme. - Chiou-Yng Lee; Che Wun Chiou; Jim-Min Lin (J. Signal Process. Syst., 2010)

Novel Mastrovito Multiplier over GF(2m) Using Trinomial. - Che Wun Chiou; Jim-Min Lin; Chiou-Yng Lee; Chi-Ting Ma (ICGEC, 2011)

Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula. - Chiou-Yng Lee; Pramod Kumar Meher (ICGEC, 2011)

Combined circuit architecture for computing normal basis and Montgomery multiplications over GF(2m). - Chiou-Yng Lee; Chia-Chen Fan; Erl-Huei Lu (Int. J. Auton. Adapt. Commun. Syst., 2011)

Multiplexer implementation of low-complexity polynomial basis multiplier in GF(m2) using all one polynomial. - Che Wun Chiou; Chiou-Yng Lee; Yun-Chi Yeh (Inf. Process. Lett., 2011)

Super Digit-Serial Systolic Multiplier over GF(2^m). - Chiou-Yng Lee (ICGEC, 2012)

A Scalable Architecture for Dual Basis GF(2m) Multiplications. - Liang-Hwa Chen; Po-Lun Chang; Yen-Ching Chang; Chiou-Yng Lee (ISBAST, 2012)

Low-complexity Gaussian normal basis multiplier over GF(2m). - Che Wun Chiou; Hung Wei Chang; Wen-Yew Liang; Chiou-Yng Lee; Jim-Min Lin; Yun-Chi Yeh (IET Inf. Secur., 2012)

Palindromic-like representation for Gaussian normal basis multiplier over GF(2m) with odd type t. - Che Wun Chiou; Tai-Pao Chuang; Shun-Shii Lin; Chiou-Yng Lee; Jim-Min Lin; Yun-Chi Yeh (IET Inf. Secur., 2012)

Fault-tolerant Gaussian normal basis multiplier over GF(2m). - Tai-Pao Chuang; Che Wun Chiou; Shun-Shii Lin; Chiou-Yng Lee (IET Inf. Secur., 2012)

Scalable Gaussian Normal Basis Multipliers over GF(2 m ) Using Hankel Matrix-Vector Representation. - Chiou-Yng Lee; Che Wun Chiou (J. Signal Process. Syst., 2012)

Pipeline Design of Bit-Parallel Gaussian Normal Basis Multiplier over GF(2m). - Che Wun Chiou; Jim-Min Lin; Yu-Ku Li; Chiou-Yng Lee; Tai-Pao Chuang; Yun-Chi Yeh (ICGEC, 2013)

Hybrid Digit-Serial Multiplier for Shifted Polynomial Basis of GF(2 m ). - Chiou-Yng Lee; Wen-Yo Lee; Che Wun Chiou; Jeng-Shyang Pan 001; Cheng-Huai Ni (ICGEC, 2013)

Digit-Serial GNB Multiplier Based on TMVP Approach over GF(2m). - Chun-Sheng Yang; Jeng-Shyang Pan 001; Chiou-Yng Lee (RVSP, 2013)

Low space-complexity digit-serial dual basis systolic multiplier over Galois field GF(2m) using Hankel matrix and Karatsuba algorithm. - Ying Yan Hua; Jim-Min Lin; Che Wun Chiou; Chiou-Yng Lee; Yong Huan Liu (IET Inf. Secur., 2013)

Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields. - Jeng-Shyang Pan 001; Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm. - Chiou-Yng Lee; Pramod Kumar Meher; Wen-Yo Lee (ISIC, 2014)

A Linear Time Pessimistic Diagnosis Algorithm for Hypermesh Multiprocessor Systems under the PMC Model. - Hong-Chun Hsu; Kuang-Shyr Wu; Cheng-Kuan Lin; Chiou-Yng Lee; Chien-Ping Chang (IEEE Trans. Computers, 2014)

Low-Latency Digit-Serial Systolic Double Basis Multiplier over $ mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach. - Jeng-Shyang Pan 001; Reza Azarderakhsh; Mehran Mozaffari Kermani; Chiou-Yng Lee; Wen-Yo Lee; Che Wun Chiou; Jim-Min Lin (IEEE Trans. Computers, 2014)

Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier. - Chiou-Yng Lee; Pramod Kumar Meher; Chien-Ping Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition. - Chiou-Yng Lee; Chun-Sheng Yang; Bimal Kumar Meher; Pramod Kumar Meher; Jeng-Shyang Pan 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures. - Siavash Bayat Sarmadi; Mehran Mozaffari Kermani; Reza Azarderakhsh; Chiou-Yng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2m). - Mehran Mozaffari Kermani; Reza Azarderakhsh; Chiou-Yng Lee; Siavash Bayat Sarmadi (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Problems on Gaussian Normal Basis Multiplication for Elliptic Curve Cryptosystem. - Che Wun Chiou; Yuh-Sien Sun; Cheng-Min Lee; Y.-L. Chiu; Jim-Min Lin; Chiou-Yng Lee (ICGEC (2), 2015)

Subquadratic Space-Complexity Parallel Systolic Multiplier Based on Karatsuba Algorithm and Block Recombination. - Chiou-Yng Lee; Che Wun Chiou; Jim-Min Lin (ICGEC (2), 2015)

Implementation of an FPGA-Based Vision Localization. - Wen-Yo Lee; Bo-Jhih Chen; Chieh-Tsai Wu; Ching-Long Shih; Ya-Hui Tsai; Yi-Chih Fan; Chiou-Yng Lee; Ti-Hung Chen (ICGEC (2), 2015)

Supporting Physical Agents in an Interactive e-book. - Jim-Min Lin; Che Wun Chiou; Chiou-Yng Lee; Jing-Rui Hsiao (ICGEC (2), 2015)

Efficient Digit-Serial Multiplier Employing Karatsuba Algorithm. - Shyan-Ming Yuan; Chiou-Yng Lee; Chia-Chen Fan (ICGEC (2), 2015)

Efficient subquadratic parallel multiplier based on modified SPB of GF(2m). - Jeng-Shyang Pan 001; Pramod Kumar Meher; Chiou-Yng Lee; Hong-Hai Bai (ISCAS, 2015)

Subquadratic space complexity Gaussian normal basis multipliers over GF(2m) based on Dickson-Karatsuba decomposition. - Jeng-Shyang Pan 001; Chiou-Yng Lee; Yao Li (IET Circuits Devices Syst., 2015)

A smart safety cane for human fall detection. - Ping-Hsu Chen; Yung-Hui Li; Che Wun Chiou; Chiou-Yng Lee; Jim-Min Lin (Int. J. Ad Hoc Ubiquitous Comput., 2015)

Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition. - Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm. - Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2m) Using Symmetric TMVP and Block Recombination Techniques. - Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach. - Chung-Hsin Liu; Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications. - Reza Azarderakhsh; Mehran Mozaffari Kermani; Siavash Bayat Sarmadi; Chiou-Yng Lee (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm". - Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach. - Chiou-Yng Lee; Pramod Kumar Meher; Chung-Hsin Liu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Hardware implementation of double basis multiplier using TMVP approach over GF (2m). - Shu-Xia Dong; Jeng-Shyang Pan 001; Chun-Sheng Yang; Chiou-Yng Lee (iCAST, 2017)

An efficient FPGA-based accelerator design for convolution. - Pengfei Song; Jeng-Shyang Pan 001; Chun-Sheng Yang; Chiou-Yng Lee (iCAST, 2017)

Gaussian normal basis multiplier over GF(2 m ) using hybrid subquadratic-and-quadratic TMVP approach for elliptic curve cryptography. - Che Wun Chiou; Yuh-Sien Sun; Cheng-Min Lee; Jim-Min Lin; Tai-Pao Chuang; Chiou-Yng Lee (IET Circuits Devices Syst., 2017)

Low-latency digit-serial dual basis multiplier for lightweight cryptosystems. - Che Wun Chiou; Chiou-Yng Lee; Jim-Min Lin; Yun-Chi Yeh; Jeng-Shyang Pan 001 (IET Inf. Secur., 2017)

Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition. - Chiou-Yng Lee; Pramod Kumar Meher; Chia-Chen Fan; Shyan-Ming Yuan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm. - Chiou-Yng Lee; Jiafeng Xie (ICCD, 2018)

Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field. - Chiou-Yng Lee; Chia-Chen Fan; Jiafeng Xie; Shyan-Ming Yuan (IEEE Access, 2018)

High-throughput Dickson basis multiplier with a trinomial for lightweight cryptosystems. - Che Wun Chiou; Cheng-Min Lee; Yuh-Sien Sun; Chiou-Yng Lee; Jim-Min Lin (IET Comput. Digit. Tech., 2018)

Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2m). - Qiliang Shao; Zhenji Hu; Shaik Nazeem Basha; Zhiping Zhang; Zhiqiang Wu 001; Chiou-Yng Lee; Jiafeng Xie (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2m) Based on Trinomials. - Jiafeng Xie; Pramod Kumar Meher; Xiaojun Zhou; Chiou-Yng Lee (IEEE Trans. Multi Scale Comput. Syst., 2018)

Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity. - Jiafeng Xie; Chiou-Yng Lee (FPGA, 2019)

LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field. - Jiafeng Xie; Chiou-Yng Lee (ACM Great Lakes Symposium on VLSI, 2019)

High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2m) based on MSPB. - Chiou-Yng Lee; Jiafeng Xie (HOST, 2019)

Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy. - Chiou-Yng Lee; Jiafeng Xie (ICCD, 2019)

Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method. - Jiafeng Xie; Chiou-Yng Lee; Pramod Kumar Meher (ISCAS, 2019)

Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm. - Chiou-Yng Lee; Jiafeng Xie (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach. - Jeng-Shyang Pan 001; Chiou-Yng Lee; Anissa Sghaier; Zeghid Medien; Jiafeng Xie (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. - Jiafeng Xie; Chiou-Yng Lee; Pramod Kumar Meher; Zhi-Hong Mao (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2m) based on Bivariate Polynomial Basis Representation. - Chiou-Yng Lee; Jiafeng Xie (ASP-DAC, 2020)

CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy. - Jiafeng Xie; Pengzhou He; Chiou-Yng Lee (ICCD, 2021)

Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber. - Yazheng Tu; Pengzhou He; Chiou-Yng Lee; Danai Chasaki; Jiafeng Xie (ISCAS, 2022)

Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor. - Chiou-Yng Lee; Medien Zeghid; Anissa Sghaier; Hassan Yousif Ahmed; Jiafeng Xie (IEEE Access, 2022)