Design and Performance of a New Multi-Lane AVI System. - M. A. Do; Chip-Hong Chang (J. Intell. Transp. Syst., 1993)

Efficient Algorithms for the Calculation of Arithmetic Spectrum from OBDD & Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean Functions. - Bogdan J. Falkowski; Chip-Hong Chang (ISCAS, 1994)

Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions. - Chip-Hong Chang; Bogdan J. Falkowski (ASP-DAC, 1995)

Generation of Multi-Polarity Arithmetic Transform from Reduced Representation of Boolean Functions. - Bogdan J. Falkowski; Chip-Hong Chang (ISCAS, 1995)

Forward and Inverse Transformations Between Haar Spectra and Ordered Binary Decision Diagrams of Boolean Functions. - Bogdan J. Falkowski; Chip-Hong Chang (IEEE Trans. Computers, 1997)

Spherical Harmonic Modeling of a 0.05 μm Base BJT: A Comparison with Monte Carlo and Asymptotic Analysis. - Chip-Hong Chang; C.-K. Lin; Neil Goldsman; Isaak D. Mayergoyz (VLSI Design, 1998)

Reed-Muller weight and literal vectors for NPN classification. - Chip-Hong Chang; Bogdan J. Falkowski (ISCAS (1), 1999)

Optimization of partially-mixed-polarity Reed-Muller expansions. - Bogdan J. Falkowski; Chip-Hong Chang (ISCAS (1), 1999)

An Efficient Algorithm for the Calculation of Generalized Adding and Arithmetic Transforms From Disjoint Cubes of Boolean Functions. - Bogdan J. Falkowski; Chip-Hong Chang (VLSI Design, 1999)

Minimization of k-Variable-Mixed-Polarity Reed-Muller Expansions. - Bogdan J. Falkowski; Chip-Hong Chang (VLSI Design, 2000)

A MSB-biased self-organizing feature map for still color image compression. - Chip-Hong Chang; Rui Xiao; Thambipillai Srikanthan (APCCAS (2), 2002)

Fuzzy-ART based digital watermarking scheme. - Chip-Hong Chang; Zhi Ye; Mingyan Zhang (APCCAS (1), 2002)

An efficient architecture for adaptive progressive thresholding. - Hui Tian; Siew Kei Lam; Thambipillai Srikanthan; Chip-Hong Chang (APCCAS (1), 2002)

On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization. - Rui Xiao; Chip-Hong Chang; Thambipillai Srikanthan (DELTA, 2002)

An interconnect optimized floorplanning of a scalar product macrocell. - Jiangmin Gu; Chip-Hong Chang; Kiat Seng Yeo (ISCAS (1), 2002)

Field programable gate array based architecture for real time image segmentation by region growing algorithm. - Chip-Hong Chang; Hui Tian; Thambipillai Srikanthan; Chai-Soon Lim (J. Electronic Imaging, 2002)

Boolean Matching Filters Based on Row and Column Weights of Reed-Muller Polarity Coefficient Matrix. - Chip-Hong Chang; Bogdan J. Falkowski (VLSI Design, 2002)

An adaptive initialization technique for color quantization by self organizing feature map. - Chip-Hong Chang; Rui Xiao; Thambipillai Srikanthan (ICASSP (3), 2003)

Low voltage, low power (5: 2) compressor cell for fast arithmetic circuits. - Jiangmin Gu; Chip-Hong Chang (ICASSP (2), 2003)

New efficient residue-to-binary converters for 4-moduli set {2n - 1, 2n, 2n + 1, 2n+1 - 1}. - Bin Cao; Chip-Hong Chang; Thambipillai Srikanthan (ISCAS (4), 2003)

Design of a high speed reverse converter for a new 4-moduli set residue number system. - Bin Cao; Thambipillai Srikanthan; Chip-Hong Chang (ISCAS (4), 2003)

Ultra low voltage, low power 4-2 compressor for high speed multiplications. - Jiangmin Gu; Chip-Hong Chang (ISCAS (5), 2003)

FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging. - Shibu Menon; Chip-Hong Chang; Rui Xiao (ISCAS (2), 2003)

A novel hybrid pass logic with static CMOS output drive full-adder cell. - Mingyan Zhang; Jiangmin Gu; Chip-Hong Chang (ISCAS (5), 2003)

A New Method for Eye Extraction from Facial Image. - Xiaoyun Deng; Chip-Hong Chang; Erwin Brandle (DELTA, 2004)

Local Search Method for FIR Filter Coefficients Synthesis. - Zhi Ye; Chip-Hong Chang (DELTA, 2004)

Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture. - Zhi Ye; Ravi Kumar Satzoda; Udit Sharma; Naveen Nazimudeen; Chip-Hong Chang (DELTA, 2004)

Efficient algorithms for common subexpression elimination in digital filter design. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (ICASSP (5), 2004)

Design of residue-to-binary converter for a new 5-moduli superset residue number system. - Bin Cao; Thambipillai Srikanthan; Chip-Hong Chang (ISCAS (2), 2004)

Frequency sensitive self-organizing maps and its application in color quantization. - Chip-Hong Chang; Pengfei Xu 009 (ISCAS (5), 2004)

Self-organizing topological tree. - Pengfei Xu 009; Chip-Hong Chang (ISCAS (5), 2004)

HWP: a new insight into canonical signed digit. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (ISCAS (5), 2004)

A new contention resolution algorithm for the design of minimal logic depth multiplierless filters. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (ISCAS (3), 2004)

Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits. - Chip-Hong Chang; Jiangmin Gu; Mingyan Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers. - Ravi Kumar Satzoda; Chip-Hong Chang (Asia-Pacific Computer Systems Architecture Conference, 2005)

A new formulation of fast diminished-one multioperand modulo 2n/+1 adder. - Bin Cao; Chip-Hong Chang; Thambipillai Srikanthan (ISCAS (1), 2005)

A new design method to modulo 2n-1 squaring. - Bin Cao; Thambipillai Srikanthan; Chip-Hong Chang (ISCAS (1), 2005)

A configurable dual moduli multi-operand modulo adder. - Chip-Hong Chang; Shibu Menon; Bin Cao; Thambipillai Srikanthan (ISCAS (2), 2005)

A novel multiplexer based truncated array multiplier. - Chip-Hong Chang; Ravi Kumar Satzoda; Swaminathan Sekar (ISCAS (1), 2005)

An area efficient 64-bit square root carry-select adder for low power applications. - Yajuan He; Chip-Hong Chang; Jiangmin Gu (ISCAS (4), 2005)

A novel covalent redundant binary Booth encoder. - Yajuan He; Chip-Hong Chang; Jiangmin Gu; Hossam A. H. Fahmy (ISCAS (1), 2005)

A versatile speech enhancement system based on perceptual wavelet denoising. - Yu Shao; Chip-Hong Chang (ISCAS (2), 2005)

Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition. - Yu Shao; Chip-Hong Chang (ISCAS (4), 2005)

I2CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (ISCAS (2), 2005)

An Ultra Low-power Current-mode Sense Amplifier for Sram Applications. - Zhi-Hui Kong; Kiat Seng Yeo; Chip-Hong Chang (J. Circuits Syst. Comput., 2005)

Contention resolution algorithm for common subexpression elimination in digital filter design. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Fuzzy-ART based adaptive digital watermarking scheme. - Chip-Hong Chang; Zhi Ye; Mingyan Zhang (IEEE Trans. Circuits Syst. Video Technol., 2005)

New adaptive color quantization method based on self-organizing maps. - Chip-Hong Chang; Pengfei Xu 009; Rui Xiao; Thambipillai Srikanthan (IEEE Trans. Neural Networks, 2005)

Self-organizing topological tree for online vector quantization and data clustering. - Pengfei Xu 009; Chip-Hong Chang; Andrew P. Paplinski (IEEE Trans. Syst. Man Cybern. Part B, 2005)

A review of 0.18-μm full adder performances for tree structured arithmetic circuits. - Chip-Hong Chang; Jiangmin Gu; Mingyan Zhang (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics. - Jiajia Chen 002; Chip-Hong Chang; A. Prasad Vinod 001 (APCCAS, 2006)

Kernel Extraction for Watermarking Combinational Logic Networks. - Aijiao Cui; Chip-Hong Chang (APCCAS, 2006)

A Reconfigurable Multi-Modulus Modulo Multiplier. - Shibu Menon; Chip-Hong Chang (APCCAS, 2006)

A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters. - Uwe Meyer-Bäse; Jiajia Chen 002; Chip-Hong Chang; Andrew G. Dempster (APCCAS, 2006)

Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis. - A. Prasad Vinod 001; Chip-Hong Chang; Pramod Kumar Meher; Ankita Singla (APCCAS, 2006)

Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm. - A. Prasad Vinod 001; Chip-Hong Chang; Pramod Kumar Meher; Ankita Singla (APCCAS, 2006)

Maximum likelihood disjunctive decomposition to reduced multirooted DAG for FIR filter design. - Chip-Hong Chang; Jiajia Chen 002; A. Prasad Vinod 001 (ISCAS, 2006)

Stego-signature at logic synthesis level for digital design IP protection. - Aijiao Cui; Chip-Hong Chang (ISCAS, 2006)

A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier. - Yajuan He; Chip-Hong Chang (ISCAS, 2006)

A fast kernel for unifying GF(p) and GF(2m) Montgomery multiplications in a scalable pipelined architecture. - Ravi Kumar Satzoda; Chip-Hong Chang (ISCAS, 2006)

A Kalman filter based on wavelet filter-bank and psychoacoustic modeling for speech enhancement. - Yu Shao; Chip-Hong Chang (ISCAS, 2006)

A novel hybrid neuro-wavelet system for robust speech recognition. - Yu Shao; Chip-Hong Chang (ISCAS, 2006)

A generalized perceptual time-frequency subtraction method for speech enhancement. - Yu Shao; Chip-Hong Chang (ISCAS, 2006)

Improved differential coefficients-based low power FIR filters. Part I. Fundamentals. - A. Prasad Vinod 001; Ankita Singla; Chip-Hong Chang (ISCAS, 2006)

A new integrated approach to the design of low-complexity FIR filters. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (ISCAS, 2006)

Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. - Aijiao Cui; Chip-Hong Chang (ISCAS, 2007)

Hamming weight pyramid - A new insight into canonical signed digit representation and its applications. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (Comput. Electr. Eng., 2007)

Low-power differential coefficients-based FIR filters using hardware-optimised multipliers. - A. Prasad Vinod 001; Ankita Singla; Chip-Hong Chang (IET Circuits Devices Syst., 2007)

Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Residue-to-Binary Converter for a New Five-Moduli Set. - Bin Cao; Chip-Hong Chang; Thambipillai Srikanthan (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A Generalized Time-Frequency Subtraction Method for Robust Speech Enhancement Based on Wavelet Filter Banks Modeling of Human Auditory System. - Yu Shao; Chip-Hong Chang (IEEE Trans. Syst. Man Cybern. Part B, 2007)

High-speed and low-power serial accumulator for serial/parallel multiplier. - Manas Ranjan Meher; Ching-Chuen Jong; Chip-Hong Chang (APCCAS, 2008)

A low complexity modulo 2n+1 squarer design. - Ramya Muralidharan; Chip-Hong Chang; Ching-Chuen Jong (APCCAS, 2008)

Intellectual property authentication by watermarking scan chain in design-for-testability flow. - Aijiao Cui; Chip-Hong Chang (ISCAS, 2008)

Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2m). - Ravi Kumar Satzoda; Ramya Muralidharan; Chip-Hong Chang (ISCAS, 2008)

IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. - Aijiao Cui; Chip-Hong Chang; Sofiène Tahar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Information Theoretic Approach to Complexity Reduction of FIR Filter Design. - Chip-Hong Chang; Jiajia Chen 002; Achutavarrier Prasad Vinod (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter. - Yajuan He; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Contention Resolution - A New Approach to Versatile Subexpressions Sharing in Multiple Constant Multiplications. - Fei Xu; Chip-Hong Chang; Ching-Chuen Jong (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Time-multiplexed Data Flow Graph for the Design of Configurable Multiplier Block. - Jiajia Chen 002; Chip-Hong Chang; Ching-Chuen Jong (ISCAS, 2009)

New Power Index Model for Switching Power Analysis from Adder Graph of FIR filter. - Jiajia Chen 002; Chip-Hong Chang; Hanhua Qian (ISCAS, 2009)

An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering. - Aijiao Cui; Chip-Hong Chang (ISCAS, 2009)

Optimization of Structural Adders in Fixed Coefficient Transposed Direct Form FIR Filters. - Mathias Faust; Chip-Hong Chang (ISCAS, 2009)

A Compact Current Mode Neuron Circuit with Gaussian Taper Learning Capability. - Fei Li; Chip-Hong Chang; Liter Siek (ISCAS, 2009)

Fixed and Variable Multi-modulus Squarer Architectures for Triple Moduli base of RNS. - Ramya Muralidharan; Chip-Hong Chang (ISCAS, 2009)

High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier. - Jiajia Chen 002; Chip-Hong Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

A New Redundant Binary Booth Encoding for Fast 2n-Bit Multiplier Design. - Yajuan He; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Real-time thermal management of 3D multi-core system with fine-grained cooling control. - Hanhua Qian; Xiwei Huang; Hao Yu 001; Chip-Hong Chang (3DIC, 2010)

Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication. - Mathias Faust; Chip-Hong Chang (ISCAS, 2010)

A novel counter-based low complexity inner-product architecture for high speed inputs. - Manas Ranjan Meher; Ching-Chuen Jong; Chip-Hong Chang; Jeremy Yung Shern Low (ISCAS, 2010)

Fast hard multiple generators for radix-8 Booth encoded modulo 2n-1 and modulo 2n+1 multipliers. - Ramya Muralidharan; Chip-Hong Chang (ISCAS, 2010)

On "A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters". - Chip-Hong Chang; Mathias Faust (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property. - Chip-Hong Chang; Aijiao Cui (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A Low Error and High Performance Multiplexer-Based Truncated Multiplier. - Chip-Hong Chang; Ravi Kumar Satzoda (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Low error bit width reduction for structural adders of FIR filters. - Mathias Faust; Chip-Hong Chang (ECCTD, 2011)

A hybrid watermarking scheme for sequential functions. - Aijiao Cui; Chip-Hong Chang; Li Zhang (ISCAS, 2011)

Bit-parallel Multiple Constant Multiplication using Look-Up Tables on FPGA. - Mathias Faust; Chip-Hong Chang (ISCAS, 2011)

A new RNS scaler for {2n - 1, 2n, 2n + 1}. - Jeremy Yung Shern Low; Chip-Hong Chang (ISCAS, 2011)

A simple radix-4 Booth encoded modulo 2n+1 multiplier. - Ramya Muralidharan; Chip-Hong Chang (ISCAS, 2011)

Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling. - Hanhua Qian; Xiwei Huang; Hao Yu 001; Chip-Hong Chang (J. Low Power Electron., 2011)

A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design. - Aijiao Cui; Chip-Hong Chang; Sofiène Tahar; Amr Talaat Abdel-Hamid (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set 2n - 1, 2n, 2n + 1. - Chip-Hong Chang; Jeremy Yung Shern Low (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Sign-Extension Avoidance and Word-Length Optimization by Positive-Offset Representation for FIR Filter Design. - Ruimin Huang; Chip-Hong Chang; Mathias Faust; Niklas Lotze; Yiannos Manoli (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Radix-8 Booth Encoded Modulo 2 n -1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System. - Ramya Muralidharan; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Bayesian Separation With Sparsity Promotion in Perceptual Wavelet Domain for Speech Enhancement and Hybrid Speech Recognition. - Yu Shao; Chip-Hong Chang (IEEE Trans. Syst. Man Cybern. Part A, 2011)

A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters. - Manas Ranjan Meher; Ching-Chuen Jong; Chip-Hong Chang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A post-processing scan-chain watermarking scheme for VLSI intellectual property protection. - Aijiao Cui; Chip-Hong Chang (APCCAS, 2012)

A unified {2n-1, 2n, 2n+1} RNS scaler with dual scaling constants. - Jeremy Yung Shern Low; Thian Fatt Tay; Chip-Hong Chang (APCCAS, 2012)

A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. - Howard Tang; Joshua Yung Lih Low; Jeremy Yung Shern Low; Liter Siek; Ching-Chuen Jong; Chip-Hong Chang (APCCAS, 2012)

Pipelined adder graph optimization for high speed multiple constant multiplication. - Martin Kumm; Peter Zipf; Mathias Faust; Chip-Hong Chang (ISCAS, 2012)

A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. - Joshua Yung Lih Low; Ching-Chuen Jong; Jeremy Yung Shern Low; Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2012)

State encoding watermarking for field authentication of sequential circuit intellectual property. - Li Zhang; Chip-Hong Chang (ISCAS, 2012)

Foreword. - Pak Kwong Chan; Chip-Hong Chang; Kiat Seng Yeo (J. Circuits Syst. Comput., 2012)

Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011). - Chip-Hong Chang; Howard C. Luong; Shanthi Pavan (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Dynamical Systems Guided Design and Analysis of Silicon Oscillators for Central Pattern Generators. - Fei Li; Arindam Basu; Chip-Hong Chang; Avis H. Cohen (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A VLSI Efficient Programmable Power-of-Two Scaler for 2n-1, 2n, 2n+1 RNS. - Jeremy Yung Shern Low; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture. - Manas Ranjan Meher; Ching-Chuen Jong; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Area-Power Efficient Modulo 2n-1 and Modulo 2n+1 Multipliers for {2n-1, 2n, 2n+1} Based RNS. - Ramya Muralidharan; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects. - Hanhua Qian; Hao Liang 003; Chip-Hong Chang; Wei Zhang 012; Hao Yu 001 (ASP-DAC, 2013)

Cluster-based distributed active current timer for hardware Trojan detection. - Yuan Cao 003; Chip-Hong Chang; Shoushun Chen (ISCAS, 2013)

A signed integer programmable power-of-two scaler for {2n-1, 2n, 2n+1} RNS. - Jeremy Yung Shern Low; Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2013)

Microchannel splitting and scaling for thermal balancing of liquid-cooled 3DIC. - Hanhua Qian; Chip-Hong Chang (ISCAS, 2013)

PCKGen: A Phase Change Memory based cryptographic key generator. - Le Zhang 001; Zhi-Hui Kong; Chip-Hong Chang (ISCAS, 2013)

An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits. - Hanhua Qian; Chip-Hong Chang; Hao Yu 001 (Integr., 2013)

A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli. - Jeremy Yung Shern Low; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers. - Ramya Muralidharan; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${ {2^{n}-1, 2^{n}, 2^{n}+1 }}$. - Thian Fatt Tay; Chip-Hong Chang; Jeremy Yung Shern Low (IEEE Trans. Very Large Scale Integr. Syst., 2013)

New algorithm for signed integer comparison in four-moduli superset {2n, 2n -1, 2n +1, 2n+1-1}. - Thian Fatt Tay; Chip-Hong Chang (APCCAS, 2014)

Hardware Trojan detection with linear regression based gate-level characterization. - Li Zhang; Chip-Hong Chang (APCCAS, 2014)

Leakage-resilient memory-based physical unclonable function using phase change material. - Le Zhang 001; Chip-Hong Chang; Alessandro Cabrini; Guido Torelli; Zhi-Hui Kong (ICCST, 2014)

Area-efficient and fast sign detection for four-moduli set RNS {2n -1, 2n, 2n +1, 22n +1}. - Chip-Hong Chang; Sachin Kumar 006 (ISCAS, 2014)

Design of programmable FIR filters using Canonical Double Based Number Representation. - Jiajia Chen 002; Chip-Hong Chang (ISCAS, 2014)

A new algorithm for single residue digit error correction in Redundant Residue Number System. - Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2014)

Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM. - Le Zhang 001; Xuanyao Fong; Chip-Hong Chang; Zhi-Hui Kong; Kaushik Roy 001 (ISCAS, 2014)

CMOS image sensor based physical unclonable function for smart phone security applications. - Yuan Cao 003; Siarhei S. Zalivaka; Le Zhang 001; Chip-Hong Chang; Shoushun Chen (ISIC, 2014)

Obfuscation and watermarking of FPGA designs based on constant value generators. - Vladimir V. Sergeichik; Alexander A. Ivaniuk; Chip-Hong Chang (ISIC, 2014)

A modular design of elliptic-curve point multiplication for resource constrained devices. - Wei Wei; Li Zhang; Chip-Hong Chang (ISIC, 2014)

A 0.7 V low-power fully programmable Gaussian function generator for brain-inspired Gaussian correlation associative memory. - Fei Li; Chip-Hong Chang; Arindam Basu; Liter Siek (Neurocomputing, 2014)

A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection. - Chip-Hong Chang; Li Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A Cluster-Based Distributed Active Current Sensing Circuit for Hardware Trojan Detection. - Yuan Cao 003; Chip-Hong Chang; Shoushun Chen (IEEE Trans. Inf. Forensics Secur., 2014)

A Pragmatic Per-Device Licensing Scheme for Hardware IP Cores on SRAM-Based FPGAs. - Li Zhang; Chip-Hong Chang (IEEE Trans. Inf. Forensics Secur., 2014)

Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions. - Le Zhang 001; Zhi-Hui Kong; Chip-Hong Chang; Alessandro Cabrini; Guido Torelli (IEEE Trans. Inf. Forensics Secur., 2014)

A high-speed and area-efficient sign detector for three moduli set RNS {2n, 2n-1, 2n+1}. - Sachin Kumar 006; Chip-Hong Chang (ASICON, 2015)

Efficient structural adder pipelining in transposed form FIR filters. - Mathias Faust; Martin Kumm; Chip-Hong Chang; Peter Zipf (DSP, 2015)

A new unified modular adder/subtractor for arbitrary moduli. - Thian Fatt Tay; Chip-Hong Chang (ISCAS, 2015)

Public key protocol for usage-based licensing of FPGA IP cores. - Li Zhang; Chip-Hong Chang (ISCAS, 2015)

Statistical analysis and design of 6T SRAM cell for physical unclonable function with dual application modes. - Le Zhang 001; Chip-Hong Chang; Zhi-Hui Kong; Chao Qun Liu (ISCAS, 2015)

Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction. - Linfeng Chen; Aijiao Cui; Chip-Hong Chang (IEEE Trans. Computers, 2015)

A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications. - Yuan Cao 003; Le Zhang 001; Chip-Hong Chang; Shoushun Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator. - Le Zhang 001; Xuanyao Fong; Chip-Hong Chang; Zhi-Hui Kong; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication. - Yuan Cao 003; Le Zhang 001; Siarhei S. Zalivaka; Chip-Hong Chang; Shoushun Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System. - Jiajia Chen 002; Chip-Hong Chang; Feng Feng; Weiao Ding; Jiatao Ding (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS. - Thian Fatt Tay; Chip-Hong Chang; Leonel Sousa (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell. - Le Zhang 001; Xuanyao Fong; Chip-Hong Chang; Zhi-Hui Kong; Kaushik Roy 001 (IEEE Trans. Inf. Forensics Secur., 2015)

Accelerating residue-to-binary conversion of very high cardinality moduli set for fully homomorphic encryption. - Truong Phu Truan Ho; Chip-Hong Chang (APCCAS, 2016)

Low-power, lightweight and reliability-enhanced current starved inverter based RO PUFs. - Chao Qun Liu; Yuan Cao 003; Chip-Hong Chang (APCCAS, 2016)

Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementation. - Siarhei S. Zalivaka; Alexander V. Puchkov; Vladimir P. Klybik; Alexander A. Ivaniuk; Chip-Hong Chang (ASP-DAC, 2016)

Using image sensor PUF as root of trust for birthmarking of perceptual image hash. - Yuan Cao 003; Le Zhang 001; Chip-Hong Chang (AsianHOST, 2016)

A new event-driven Dynamic Vision Sensor based Physical Unclonable Function for camera authentication in reactive monitoring system. - Yue Zheng; Yuan Cao 003; Chip-Hong Chang (AsianHOST, 2016)

A VLSI-efficient signed magnitude comparator for { 2n-1, 2n, 2n +2n+1-1} RNS. - Sachin Kumar 006; Chip-Hong Chang (ISCAS, 2016)

A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks. - Govind Narasimman; Subhrajit Roy; Xuanyao Fong; Kaushik Roy 001; Chip-Hong Chang; Arindam Basu (ISCAS, 2016)

A new scheme for secret-hiding in DSP circuits. - Sumedh Dhabu; Chip-Hong Chang (ISOCC, 2016)

Editorial. - Chip-Hong Chang; Tae-Hyoung Kim; Hao Yu 001 (J. Circuits Syst. Comput., 2016)

A Non-Iterative Multiple Residue Digit Error Detection and Correction Algorithm in RRNS. - Thian Fatt Tay; Chip-Hong Chang (IEEE Trans. Computers, 2016)

A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction. - Jiatao Ding; Jiajia Chen 002; Chip-Hong Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Hypergraph Based Minimum Arborescence Algorithm for the Optimization and Reoptimization of Multiple Constant Multiplications. - Feng Feng; Jiajia Chen 002; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory. - Yuhao Wang 002; Leibin Ni; Chip-Hong Chang; Hao Yu 001 (IEEE Trans. Inf. Forensics Secur., 2016)

A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2n-1, 2n, 2n+1}. - Sachin Kumar 006; Chip-Hong Chang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Erratum to "Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS {2n-1, 2n, 2n+1}". - Thian Fatt Tay; Chip-Hong Chang; Jeremy Yung Shern Low (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An energy-efficient true random number generator based on current starved ring oscillators. - Yuan Cao 003; Chip-Hong Chang; Yue Zheng; Xiaojin Zhao (AsianHOST, 2017)

ASHES 2017: Workshop on Attacks and Solutions in Hardware Security. - Chip-Hong Chang; Marten van Dijk; Farinaz Koushanfar; Ulrich Rührmair; Mark Tehranipoor (CCS, 2017)

A new watermarking scheme on scan chain ordering for hard IP protection. - Xiaonan Huang; Aijiao Cui; Chip-Hong Chang (ISCAS, 2017)

A new write-contention based dual-port SRAM PUF with multiple response bits per cell. - Chao Qun Liu; Yue Zheng; Chip-Hong Chang (ISCAS, 2017)

20 Years of research on intellectual property protection. - Miodrag Potkonjak; Gang Qu 001; Farinaz Koushanfar; Chip-Hong Chang (ISCAS, 2017)

Current mirror array: A novel lightweight strong PUF topology with enhanced reliability. - Zheng Wang 027; Yi Chen 012; Aakash Patil; Chip-Hong Chang; Arindam Basu (ISCAS, 2017)

Low-cost fortification of arbiter PUF against modeling attack. - Siarhei S. Zalivaka; Alexander A. Ivaniuk; Chip-Hong Chang (ISCAS, 2017)

A novel scheme for information hiding at physical layer of wireless communications. - Sumedh Dhabu; Chip-Hong Chang (ISOCC, 2017)

FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability. - Siarhei S. Zalivaka; Alexander A. Ivaniuk; Chip-Hong Chang (ISQED, 2017)

A New Cost-Aware Sensitivity-Driven Algorithm for the Design of FIR Filters. - Jiajia Chen 002; Jinghong Tan; Chip-Hong Chang; Feng Feng (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

New Algorithm for Signed Integer Comparison in {2n+k, 2n-1, 2n+1, 2n±1-1} and Its Efficient Hardware Implementation. - Sachin Kumar 006; Chip-Hong Chang; Thian Fatt Tay (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function. - Chao Qun Liu; Yuan Cao 003; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks. - Aijiao Cui; Yanhui Luo; Chip-Hong Chang (IEEE Trans. Inf. Forensics Secur., 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Scaling-Assisted Signed Integer Comparator for the Balanced Five-Moduli Set RNS 2n-1, 2n, 2n+ 1, 2n+1-1, 2n-1-1. - Sachin Kumar 006; Chip-Hong Chang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

ASHES 2018- Workshop on Attacks and Solutions in Hardware Security. - Chip-Hong Chang; Jorge Guajardo; Daniel E. Holcomb; Francesco Regazzoni 001; Ulrich Rührmair (CCS, 2018)

A Fully Digital Physical Unclonable Function Based Temperature Sensor for Secure Remote Sensing. - Yuan Cao 003; Yunyi Guo; Benyu Liu; Wei Ge; Min Zhu 001; Chip-Hong Chang (ICCCN, 2018)

Facial biohashing based user-device physical unclonable function for bring your own device security. - Yue Zheng; Yuan Cao 003; Chip-Hong Chang (ICCE, 2018)

Towards Ideal Lattice-Based Cryptography on ASIC: A Custom Implementation of Number Theoretic Transform. - Truong Phu Truan Ho; Chip-Hong Chang (DSP, 2018)

A Current Comparator Based Physical Unclonable Function with High Reliability and Energy Efficiency. - Qiang Zhao; Yuan Cao 003; Xiaojin Zhao; Chip-Hong Chang (DSP, 2018)

A Sub-pico Joules Per Bit Robust Physical Unclonable Function Based on Subthreshold Voltage References. - Yuan Cao 003; Chip-Hong Chang; Wenhan Zheng; Xiaojin Zhao (ISCAS, 2018)

Active IC Metering of Digital Signal Processing Subsystem with Two-Tier Activation for Secure Split Test. - Sumedh Somnath Dhabu; Yue Zheng; Wenye Liu; Chip-Hong Chang (ISCAS, 2018)

Securing IoT Monitoring Device using PUF and Physical Layer Authentication. - Yue Zheng; Sumedh Somnath Dhabu; Chip-Hong Chang (ISCAS, 2018)

New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications. - Jiajia Chen 002; Chip-Hong Chang; Yujia Wang; Juan Zhao 005; Susanto Rahardja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Low Power Diode-Clamped Inverter-Based Strong Physical Unclonable Function for Robust and Lightweight Authentication. - Yuan Cao 003; Chao Qun Liu; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters. - Jiajia Chen 002; Chip-Hong Chang; Jiatao Ding; Rui Qiao; Mathias Faust (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning. - Zheng Wang 027; Yi Chen 012; Aakash Patil; Jayasanker Jayabalan; Xueyong Zhang; Chip-Hong Chang; Arindam Basu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A New Accurate and Fast Homography Computation Algorithm for Sports and Traffic Video Analysis. - ShuMin Liu; Jiajia Chen 002; Chip-Hong Chang; Ye Ai (IEEE Trans. Circuits Syst. Video Technol., 2018)

A Modeling Attack Resistant Deception Technique for Securing PUF based Authentication. - Chongyan Gu; Chip-Hong Chang; Weiqiang Liu 001; Shichao Yu; Qingqing Ma; Máire O'Neill (AsianHOST, 2019)

Identification of State Registers of FSM Through Full Scan by Data Analytics. - Chengkang He; Aijiao Cui; Chip-Hong Chang (AsianHOST, 2019)

Vulnerability Analysis on Noise-Injection Based Hardware Attack on Deep Neural Networks. - Wenye Liu; Si Wang; Chip-Hong Chang (AsianHOST, 2019)

Detecting Adversarial Examples for Deep Neural Networks via Layer Directed Discriminative Noise Injection. - Si Wang; Wenye Liu; Chip-Hong Chang (AsianHOST, 2019)

ASHES 2019: 3rd Workshop on Attacks and Solutions in Hardware Security. - Chip-Hong Chang; Daniel E. Holcomb; Francesco Regazzoni 001; Ulrich Rührmair; Patrick Schaumont (CCS, 2019)

A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs. - Chongyan Gu; Chip-Hong Chang; Weiqiang Liu 001; Neil Hanley; Jack Miskelly; Máire O'Neill (ASHES@CCS, 2019)

Analysis of Circuit Aging on Accuracy Degradation of Deep Neural Network Accelerator. - Wenye Liu; Chip-Hong Chang (ISCAS, 2019)

High-Speed True Random Number Generator Based on Differential Current Starved Ring Oscillators with Improved Thermal Stability. - Kai Wang; Yuan Cao 003; Chip-Hong Chang; Xiaoli Ji (ISCAS, 2019)

An In-Pixel Gain Amplifier Based Event-Driven Physical Unclonable Function for CMOS Dynamic Vision Sensors. - Biyin Wang; Xiaojin Zhao; Yue Zheng; Chip-Hong Chang (ISCAS, 2019)

A Reliable Physical Unclonable Function Based on Differential Charging Capacitors. - Hang Yuan; Wei Guo 018; Chip-Hong Chang; Yuan Cao 003; Shaojun Wei; Shouyi Yin; Chenchen Deng; Leibo Liu; Wei Ge; Fan Zhang 044 (ISCAS, 2019)

An Energy-Efficient Current-Starved Inverter Based Strong Physical Unclonable Function With Enhanced Temperature Stability. - Yuan Cao 003; Wenhan Zheng; Xiaojin Zhao; Chip-Hong Chang (IEEE Access, 2019)

Area- and Power-Efficient Nearly-Linear Phase Response IIR Filter by Iterative Convex Optimization. - Gelei Deng; Jiajia Chen 002; Jiaxuan Zhang; Chip-Hong Chang (IEEE Access, 2019)

Emerging Attacks and Solutions for Secure Hardware in the Internet of Things. - Chip-Hong Chang; Marten van Dijk; Ulrich Rührmair; Mark Tehranipoor (IEEE Trans. Dependable Secur. Comput., 2019)

UDhashing: Physical Unclonable Function-Based User-Device Hash for Endpoint Authentication. - Yue Zheng; Yuan Cao 003; Chip-Hong Chang (IEEE Trans. Ind. Electron., 2019)

Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response. - Siarhei S. Zalivaka; Alexander A. Ivaniuk; Chip-Hong Chang (IEEE Trans. Inf. Forensics Secur., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

ASHES 2020: 4th Workshop on Attacks and Solutions in Hardware Security. - Chip-Hong Chang; Stefan Katzenbeisser 001; Ulrich Rührmair; Patrick Schaumont (CCS, 2020)

Imperceptible Misclassification Attack on Deep Learning Accelerator by Glitch Injection. - Wenye Liu; Chip-Hong Chang; Fan Zhang 010; Xiaoxuan Lou (DAC, 2020)

Reducing Temperature Induced Unreliability in Sub-Threshold Strong PUFs through Circuit Modeling. - Nimesh Shah; Sumon Kumar Bose; Chip-Hong Chang; Arindam Basu (ISCAS, 2020)

Fired Neuron Rate Based Decision Tree for Detection of Adversarial Examples in DNNs. - Si Wang; Wenye Liu; Chip-Hong Chang (ISCAS, 2020)

A PUF-Based Data-Device Hash for Tampered Image Detection and Source Camera Identification. - Yue Zheng; Yuan Cao 003; Chip-Hong Chang (IEEE Trans. Inf. Forensics Secur., 2020)

Ed-PUF: Event-Driven Physical Unclonable Function for Camera Authentication in Reactive Monitoring System. - Yue Zheng; Xiaojin Zhao; Takashi Sato 001; Yuan Cao 003; Chip-Hong Chang (IEEE Trans. Inf. Forensics Secur., 2020)

A New Polarization Image Demosaicking Algorithm by Exploiting Inter-Channel Correlations With Guided Filtering. - ShuMin Liu; Jiajia Chen 002; Yuan Xun; Xiaojin Zhao; Chip-Hong Chang (IEEE Trans. Image Process., 2020)

A 1036-F2/Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF. - Qiang Zhao; Yiheng Wu; Xiaojin Zhao; Yuan Cao 003; Chip-Hong Chang (IEEE Trans. Very Large Scale Integr. Syst., 2020)

An Ultra-Low Power 3-T Chaotic Map based True Random Number Generator. - Lijuan Han; Yuan Cao 003; Lei Qian; Haodong Xie; Chip-Hong Chang (AsianHOST, 2021)

A Forward Error Compensation Approach for Fault Resilient Deep Neural Network Accelerator Design. - Wenye Liu; Chip-Hong Chang (ASHES@CCS, 2021)

Live Demonstration: Event-Driven Physical Unclonable Function for Proactive Monitoring System by Dynamic Vision Sensor. - Jian Xian Soo; Yue Zheng; Chip-Hong Chang (ISCAS, 2021)

Fingerprinting Deep Neural Networks - a DeepFool Approach. - Si Wang; Chip-Hong Chang (ISCAS, 2021)

Secure Mutual Authentication and Key-Exchange Protocol between PUF-Embedded IoT Endpoints. - Yue Zheng; Chip-Hong Chang (ISCAS, 2021)

Hardware Security in Emerging Technologies: Vulnerabilities, Attacks, and Solutions. - Naghmeh Karimi; Kanad Basu; Chip-Hong Chang; Jason M. Fung (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security. - Wenye Liu; Chip-Hong Chang; Xueyang Wang; Chen Liu 013; Jason M. Fung; Mohammad Ebrahimabadi; Naghmeh Karimi; Xingyu Meng; Kanad Basu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

A New Lightweight In Situ Adversarial Sample Detector for Edge Deep Neural Network. - Si Wang; Wenye Liu; Chip-Hong Chang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

The ASHES 2019 special issue at JCEN. - Chip-Hong Chang; Daniel E. Holcomb; Ulrich Rührmair; Patrick Schaumont (J. Cryptogr. Eng., 2021)

A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs. - Chongyan Gu; Chip-Hong Chang; Weiqiang Liu 001; Neil Hanley; Jack Miskelly; Máire O'Neill (J. Cryptogr. Eng., 2021)

A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication. - Chongyan Gu; Chip-Hong Chang; Weiqiang Liu 001; Shichao Yu; Yale Wang; Máire O'Neill (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools. - Wei Hu 008; Chip-Hong Chang; Anirban Sengupta; Swarup Bhunia; Ryan Kastner; Hai Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A New PUF Based Lock and Key Solution for Secure In-Field Testing of Cryptographic Chips. - Aijiao Cui; Chip-Hong Chang; Wei Zhou; Yue Zheng (IEEE Trans. Emerg. Top. Comput., 2021)

Identification of FSM State Registers by Analytics of Scan-Dump Data. - Aijiao Cui; Chengkang He; Chip-Hong Chang; Hao Lu (IEEE Trans. Inf. Forensics Secur., 2021)

Stealthy and Robust Glitch Injection Attack on Deep Learning Accelerator for Target With Variational Viewpoint. - Wenye Liu; Chip-Hong Chang; Fan Zhang 010 (IEEE Trans. Inf. Forensics Secur., 2021)

A Buyer-traceable DNN Model IP Protection Method Against Piracy and Misappropriation. - Si Wang; Chaohui Xu; Yue Zheng; Chip-Hong Chang (AICAS, 2022)

Deep Texture-Depth-Based Attention for Face Recognition on IoT Devices. - Yuxin Lin; Wenye Liu; Chip-Hong Chang (APCCAS, 2022)

ASHES 2022 - 6th Workshop on Attacks and Solutions in Hardware Security. - Chip-Hong Chang; Domenic Forte; Debdeep Mukhopadhyay; Ulrich Rührmair (CCS, 2022)

A Practical Man-in-the-Middle Attack on Deep Learning Edge Device by Sparse Light Strip Injection into Camera Data Lane. - Wenye Liu; Weiyang He; Bowen Hu; Chip-Hong Chang (SOCC, 2022)

Inconspicuous Data Augmentation Based Backdoor Attack on Deep Neural Networks. - Chaohui Xu; Wenye Liu; Yue Zheng; Si Wang; Chip-Hong Chang (SOCC, 2022)

The ASHES 2020 special issue at JCEN. - Chip-Hong Chang; Stefan Katzenbeisser 001; Ulrich Rührmair; Patrick Schaumont (J. Cryptogr. Eng., 2022)

Radio Frequency Fingerprints vs. Physical Unclonable Functions - Are They Twins, Competitors, or Allies? - Junqing Zhang; Chip-Hong Chang; Chongyan Gu; Lajos Hanzo (IEEE Netw., 2022)

Area, Time and Energy Efficient Multicore Hardware Accelerators for Extended Merkle Signature Scheme. - Yuan Cao 003; Yanze Wu; Lan Qin; Shuai Chen; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme. - Yuan Cao 003; Yanze Wu; Wen Wang 007; Xu Lu; Shuai Chen; Jing Ye 001; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A New Energy-Efficient and High Throughput Two-Phase Multi-Bit per Cycle Ring Oscillator-Based True Random Number Generator. - Yuan Cao 003; Xiaojin Zhao; Wenhan Zheng; Yue Zheng; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A DNN Fingerprint for Non-Repudiable Model Ownership Identification and Piracy Detection. - Yue Zheng; Si Wang; Chip-Hong Chang (IEEE Trans. Inf. Forensics Secur., 2022)

Zero-Shot Text Classification via Self-Supervised Tuning. - Chaoqun Liu; Wenxuan Zhang 001; Guizhen Chen; Xiaobao Wu; Anh Tuan Luu; Chip-Hong Chang; Lidong Bing (ACL (Findings), 2023)

An Empirical Study of the Inherent Resistance of Knowledge Distillation Based Federated Learning to Targeted Poisoning Attacks. - Weiyang He; Zizhen Liu; Chip-Hong Chang (ATS, 2023)

ASHES '23: Workshop on Attacks and Solutions in Hardware Security. - Lejla Batina; Chip-Hong Chang; Domenic Forte; Ulrich Rührmair (CCS, 2023)

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. - Jianan Mu; Huajie Tan; Jiawen Wu; Haotian Lu 002; Chip-Hong Chang; Shuai Chen; Shengwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2023)

MERCURY: An Automated Remote Side-channel Attack to Nvidia Deep Learning Accelerator. - Xiaobei Yan; Xiaoxuan Lou; Guowen Xu; Han Qiu 001; Shangwei Guo; Chip-Hong Chang; Tianwei Zhang 004 (ICFPT, 2023)

White-Box Adversarial Attacks on Deep Learning-Based Radio Frequency Fingerprint Identification. - Jie Ma; Junqing Zhang; Guanxiong Shen; Alan Marshall 001; Chip-Hong Chang (ICC, 2023)

Hardware-efficient Softmax Approximation for Self-Attention Networks. - Nazim Altar Koca; Anh Tuan Do; Chip-Hong Chang (ISCAS, 2023)

A Lightweight PUF-based Secure Group Key Agreement Protocol for Wireless Sensor Networks. - Yue Zheng; Wenye Liu; Chip-Hong Chang (ISCAS, 2023)

Defense against ML-based Power Side-channel Attacks on DNN Accelerators with Adversarial Attacks. - Xiaobei Yan; Chip-Hong Chang; Tianwei Zhang 004 (CoRR, 2023)

PUF-Based Mutual Authentication and Key Exchange Protocol for Peer-to-Peer IoT Applications. - Yue Zheng; Wenye Liu; Chongyan Gu; Chip-Hong Chang (IEEE Trans. Dependable Secur. Comput., 2023)

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. - Jianan Mu; Yi Ren; Wen Wang 007; Yizhong Hu; Shuai Chen; Chip-Hong Chang; Junfeng Fan; Jing Ye 001; Yuan Cao 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

The ASHES 2021 special issue at JCEN. - Chip-Hong Chang; Stefan Katzenbeisser 001; Debdeep Mukhopadhyay; Ulrich Rührmair (J. Cryptogr. Eng., 2023)

A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration. - Yuan Cao 003; Wanyi Liu; Yue Zheng; Shuai Chen; Jing Ye 001; Lei Qian; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Guest Editorial Special Issue on the Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022). - Chip-Hong Chang; Pingqiang Zhou; Yuan Cao 003; Qiang Liu 011 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An Imperceptible Data Augmentation Based Blackbox Clean-Label Backdoor Attack on Deep Neural Networks. - Chaohui Xu; Wenye Liu; Yue Zheng; Si Wang; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Effect of Line Resistance of Passive Memristive Crossbars on Spiking Neural Network Performance. - Pierre Lewden; Adrien F. Vincent; Jean Tomas; Chip-Hong Chang; Sylvain Saïghi (AICAS, 2024)

GaitSpike: Event-based Gait Recognition With Spiking Neural Network. - Ying Tao; Chip-Hong Chang; Sylvain Saïghi; Shengyu Gao (AICAS, 2024)

A Black-Box Targeted Misclassification Attack on Edge AI with Adversarial Examples Generated from RAW Image Sensor Data. - Bowen Hu; Weiyang He; Kuo Wang; Chip-Hong Chang (AsianHOST, 2024)

ASHES '24: Workshop on Attacks and Solutions in Hardware Security. - Lejla Batina; Chip-Hong Chang; Ulrich Rührmair; Jakub Szefer (CCS, 2024)

Steganographic Passport: An Owner and User Verifiable Credential for Deep Model IP Protection Without Retraining. - Qi Cui; Ruohan Meng; Chaohui Xu; Chip-Hong Chang (CVPR, 2024)

Efficient Fast Additive Homomorphic Encryption Cryptoprocessor for Privacy-Preserving Federated Learning Aggregation. - Wenye Liu; Nazim Altar Koca; Chip-Hong Chang (DATE, 2024)

Live Demonstration: Man-in-the-Middle Attack on Edge Artificial Intelligence. - Bowen Hu; Weiyang He; Si Wang; Wenye Liu; Chip-Hong Chang (ISCAS, 2024)

Exploring Error Correction Circuits on RISC-V based Systems for Space Applications. - Nazim Altar Koca; Chip-Hong Chang; Anh Tuan Do; Vishnu P. Nambiar (ISCAS, 2024)

An In-Sensor PUF Featuring Optical Reconfigurability and Near-100% Hardware Reuse Ratio for Trustworthy Sensing. - Haibiao Zuo; Xiaoliang Huang; Shiqiao Zhang; Chip-Hong Chang; Xiaojin Zhao (VLSI Technology and Circuits, 2024)

LTE: Lightweight and Time-Efficient Hardware Encoder for Post-Quantum Scheme HQC. - Yazheng Tu; Pengzhou He; Chip-Hong Chang; Jiafeng Xie (IEEE Comput. Archit. Lett., 2024)

BadHMP: Backdoor Attack against Human Motion Prediction. - Chaohui Xu; Si Wang; Chip-Hong Chang (CoRR, 2024)

IDEA: An Inverse Domain Expert Adaptation Based Active DNN IP Protection Method. - Chaohui Xu; Qi Cui; Jinxin Dong; Weiyang He; Chip-Hong Chang (CoRR, 2024)

DFREC: DeepFake Identity Recovery Based on Identity-aware Masked Autoencoder. - Peipeng Yu; Hui Gao; Zhitao Huang; Zhihua Xia; Chip-Hong Chang (CoRR, 2024)

SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks. - Zizhen Liu; Weiyang He; Chip-Hong Chang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Inf. Forensics Secur., 2024)

Security and Functional Safety for AI in Embedded Automotive System - A Tutorial. - Yi Wang 016; Jing Xiao; Zhengzhe Wei; Yuanjin Zheng; Kea-Tiong Tang; Chip-Hong Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Diffense: Defense Against Backdoor Attacks on Deep Neural Networks With Latent Diffusion. - Bowen Hu; Chip-Hong Chang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

Guest Editorial: Toward Trustworthy AI: Advances in Circuits, Systems, and Applications. - Shih-Hsu Huang; Pin-Yu Chen; Stjepan Picek; Chip-Hong Chang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

An Overview of Trustworthy AI: Advances in IP Protection, Privacy-Preserving Federated Learning, Security Verification, and GAI Safety Alignment. - Yue Zheng; Chip-Hong Chang; Shih-Hsu Huang; Pin-Yu Chen; Stjepan Picek (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

PUF-based Edge DNN Model IP Protection with Self-obfuscation and Publicly Verifiable Ownership. - Jingdong Jiang; Yue Zheng; Chip-Hong Chang (ISCAS, 2025)

Accuracy-preserving Layer Normalization Approximations for Efficient Transformer Hardware Accelerators. - Nazim Altar Koca; Anh Tuan Do; Chip-Hong Chang (ISCAS, 2025)

Unlocking the Capabilities of Vision-Language Models for Generalizable and Explainable Deepfake Detection. - Peipeng Yu; Jianwei Fei; Hui Gao; Xuan Feng; Zhihua Xia; Chip-Hong Chang (CoRR, 2025)

HAST: A Hardware-Efficient Spatio-Temporal Correlation Near-Sensor Noise Filter for Dynamic Vision Sensors. - Pradeep Kumar Gopalakrishnan; Chip-Hong Chang; Arindam Basu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

CHIP: Chameleon Hash-based Irreversible Passport for Robust Deep Model Ownership Verification and Active Usage Control. - Chaohui Xu; Qi Cui; Chip-Hong Chang (CoRR, 2025)

HASSLE: A Self-Supervised Learning Enhanced Hijacking Attack on Vertical Federated Learning. - Weiyang He; Chip-Hong Chang (CoRR, 2025)