A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications. - Chao-Tsung Huang; Mehul Tikekar; Chiraag Juvekar; Vivienne Sze; Anantha P. Chandrakasan (ISSCC, 2013)

HEVC interpolation filter architecture for quad full HD decoding. - Chao-Tsung Huang; Chiraag Juvekar; Mehul Tikekar; Anantha P. Chandrakasan (VCIP, 2013)

A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications. - Mehul Tikekar; Chao-Tsung Huang; Chiraag Juvekar; Vivienne Sze; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2014)

Decoder Hardware Architecture for HEVC. - Mehul Tikekar; Chao-Tsung Huang; Chiraag Juvekar; Vivienne Sze; Anantha P. Chandrakasan (High Efficiency Video Coding, 2014)

16.2 A Keccak-based wireless authentication tag with per-query key update and power-glitch attack countermeasures. - Chiraag Juvekar; Hyung-Min Lee; Joyce Kwong; Anantha P. Chandrakasan (ISSCC, 2016)

eeDTLS: Energy-Efficient Datagram Transport Layer Security for the Internet of Things. - Utsav Banerjee; Chiraag Juvekar; Samuel H. Fuller; Anantha P. Chandrakasan (GLOBECOM, 2017)

21.8 An actively detuned wireless power receiver with public key cryptographic authentication and dynamic power allocation. - Nachiket V. Desai; Chiraag Juvekar; Shubham Chandak; Anantha P. Chandrakasan (ISSCC, 2017)

A Nonvolatile Flip-Flop-Enabled Cryptographic Wireless Authentication Tag With Per-Query Key Update and Power-Glitch Attack Countermeasures. - Hyung-Min Lee; Chiraag Juvekar; Joyce Kwong; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2017)

An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications. - Utsav Banerjee; Chiraag Juvekar; Andrew Wright; Arvind 001; Anantha P. Chandrakasan (ISSCC, 2018)

GAZELLE: A Low Latency Framework for Secure Neural Network Inference. - Chiraag Juvekar; Vinod Vaikuntanathan; Anantha P. Chandrakasan (IACR Cryptol. ePrint Arch., 2018)

An Actively Detuned Wireless Power Receiver With Public Key Cryptographic Authentication and Dynamic Power Allocation. - Nachiket V. Desai; Chiraag Juvekar; Shubham Chandak; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2018)

Hardware and protocols for authentication and secure computation. - Chiraag Shashikant Juvekar (2018)

Reconstructing Network Inputs with Additive Perturbation Signatures. - Nick Moran; Chiraag Juvekar (CoRR, 2019)

An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications. - Utsav Banerjee; Andrew Wright; Chiraag Juvekar; Madeleine Waller; Arvind 001; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2019)

29.8 THzID: A 1.6mm2 Package-Less Cryptographic Identification Tag with Backscattering and Beam-Steering at 260GHz. - Mohamed I. Ibrahim; Muhammad Ibrahim Wasiq Khan; Wanyeong Jung; Rabia Tugce Yazicigil; Chiraag Shashikant Juvekar; Anantha P. Chandrakasan; Ruonan Han 001 (ISSCC, 2020)

Fast Vector Oblivious Linear Evaluation from Ring Learning with Errors. - Leo de Castro; Chiraag Juvekar; Vinod Vaikuntanathan (IACR Cryptol. ePrint Arch., 2020)

Does Fully Homomorphic Encryption Need Compute Acceleration? - Leo de Castro; Rashmi Agrawal 001; Rabia Tugce Yazicigil; Anantha P. Chandrakasan; Vinod Vaikuntanathan; Chiraag Juvekar; Ajay Joshi (IACR Cryptol. ePrint Arch., 2021)

CMOS THz-ID: A 1.6-mm² Package-Less Identification Tag Using Asymmetric Cryptography and 260-GHz Far-Field Backscatter Communication. - Muhammad Ibrahim Wasiq Khan; Mohamed I. Ibrahim; Chiraag Shashikant Juvekar; Wanyeong Jung; Rabia Tugce Yazicigil; Anantha P. Chandrakasan; Ruonan Han 001 (IEEE J. Solid State Circuits, 2021)

Security Assessment of Phase-Based Ranging Systems in a Multipath Environment. - Arslan Riaz; Dylan Nash; Jonathan Ngo; Chiraag Juvekar; Phillip M. Nadeau; Tao Yu; Rabia Tugce Yazicigil (ACM J. Emerg. Technol. Comput. Syst., 2022)

FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption. - Rashmi Agrawal 001; Leo de Castro; Guowei Yang 005; Chiraag Juvekar; Rabia Tugce Yazicigil; Anantha P. Chandrakasan; Vinod Vaikuntanathan; Ajay Joshi (HPCA, 2023)

MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic Encryption. - Rashmi Agrawal 001; Leo de Castro; Chiraag Juvekar; Anantha P. Chandrakasan; Vinod Vaikuntanathan; Ajay Joshi (MICRO, 2023)

Writing a Good Security Paper for ISSCC (2025). - Utsav Banerjee; Chiraag Juvekar; Yong Ki Lee; Leibo Liu; Sanu Mathew; Thomas Pöppelmann; Shreyas Sen; Takeshi Sugawara 001; Ingrid Verbauwhede; Rabia Tugce Yazicigil (CoRR, 2025)