Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design. - Mozammel Hossain; Chirag Desai; Tom Chen 001; Vikas Agarwal (Integr., 2015)

Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time. - Debashis Mandal; Chirag Desai; Bertan Bakkaloglu; Sayfe Kiaei (IEEE Trans. Circuits Syst. II Express Briefs, 2019)