FPGA power reduction by guarded evaluation. - Jason Helge Anderson; Chirag Ravishankar (FPGA, 2010)

Parallel FPGA technology mapping using multi-core architectures. - Andrew A. Kennings; Chirag Ravishankar (CCECE, 2011)

EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only). - Sundaram Ananthanarayanan; Chirag Ravishankar; Siddharth Garg; Andrew A. Kennings (FPGA, 2012)

EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip. - Chirag Ravishankar; Sundaram Ananthanarayanan; Siddharth Garg; Andrew A. Kennings (FPL, 2012)

Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms. - Chirag Ravishankar; Sundaram Ananthanarayanan; Siddharth Garg; Andrew A. Kennings (ISQED, 2012)

FPGA power reduction by guarded evaluation considering physical information. - Chirag Ravishankar; Andrew A. Kennings; Jason Helge Anderson (VLSI-SoC, 2012)

FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. - Chirag Ravishankar; Jason Helge Anderson; Andrew A. Kennings (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Raising FPGA Logic Density Through Synthesis-Inspired Architecture. - Jason Helge Anderson; Qiang Wang; Chirag Ravishankar (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Placement Strategies for 2.5D FPGA Fabric Architectures. - Chirag Ravishankar; Dinesh Gaitonde; Trevor Bauer (FPL, 2018)

SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs. - Chirag Ravishankar; Henri Fraisse; Dinesh Gaitonde (FPT, 2018)

Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture. - Brian Gaide; Dinesh Gaitonde; Chirag Ravishankar; Trevor Bauer (FPGA, 2019)

Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. - Abhishek Kumar Jain; Chirag Ravishankar; Hossein Omidian; Sharan Kumar; Maithilee Kulkarni; Aashish Tripathi; Dinesh Gaitonde (FCCM, 2023)

Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. - Shashwat Shrivastava; Stefan Nikolic 001; Chirag Ravishankar; Dinesh Gaitonde; Mirjana Stojilovic (FPGA, 2023)

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. - Shashwat Shrivastava; Stefan Nikolic 001; Chirag Ravishankar; Dinesh Gaitonde; Mirjana Stojilovic (ICCAD, 2023)

Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox. - Shashwat Shrivastava; Stefan Nikolic 001; Sun Tanaka; Chirag Ravishankar; Dinesh Gaitonde; Mirjana Stojilovic (FCCM, 2025)