Improving the error behavior of DRAM by exploiting its Z-channel property. - Kira Kraft; Chirag Sudarshan; Deepak M. Mathew; Christian Weis; Norbert Wehn; Matthias Jung 001 (DATE, 2018)

An analysis on retention error behavior and power consumption of recent DDR4 DRAMs. - Deepak M. Mathew; Martin Schultheis; Carl Christian Rheinländer; Chirag Sudarshan; Christian Weis; Norbert Wehn; Matthias Jung 001 (DATE, 2018)

The Role of Memories in Transprecision Computing. - Christian Weis; Matthias Jung 001; Éder F. Zulian; Chirag Sudarshan; Deepak M. Mathew; Norbert Wehn (ISCAS, 2018)

Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving. - Matthias Jung 001; Sally A. McKee; Chirag Sudarshan; Christoph Dropmann; Christian Weis; Norbert Wehn (MEMSYS, 2018)

Efficient coding scheme for DDR4 memory subsystems. - Kira Kraft; Deepak M. Mathew; Chirag Sudarshan; Matthias Jung 001; Christian Weis; Norbert Wehn; Florian Longnos (MEMSYS, 2018)

An In-DRAM Neural Network Processing Engine. - Chirag Sudarshan; Jan Lappas; Muhammad Mohsin Ghaffar; Vladimir Rybalkin; Christian Weis; Matthias Jung 001; Norbert Wehn (ISCAS, 2019)

Fast validation of DRAM protocols with timed petri nets. - Matthias Jung 001; Kira Kraft; Taha Soliman; Chirag Sudarshan; Christian Weis; Norbert Wehn (MEMSYS, 2019)

Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements. - Sven Müelich; Sebastian Bitzer; Chirag Sudarshan; Christian Weis; Norbert Wehn; Martin Bossert; Robert F. H. Fischer (REDUNDANCY, 2019)

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing. - Chirag Sudarshan; Jan Lappas; Christian Weis; Deepak M. Mathew; Matthias Jung 001; Norbert Wehn (SAMOS, 2019)

eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. - Dimitrios Stathis 001; Chirag Sudarshan; Yu Yang; Matthias Jung 001; Syed Mohammad Asad Hassan Jafri; Christian Weis; Ahmed Hemani; Anders Lansner; Norbert Wehn (CoRR, 2019)

A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions. - Muhammad Mohsin Ghaffar; Chirag Sudarshan; Christian Weis; Matthias Jung 001; Norbert Wehn (MEMSYS, 2020)

Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory. - Sven Müelich; Chirag Sudarshan; Christian Weis; Martin Bossert; Robert F. H. Fischer; Norbert Wehn (MEMSYS, 2020)

Efficient Generation of Application Specific Memory Controllers. - Marco V. Natale; Matthias Jung 001; Kira Kraft; Frederik Lauer; Johannes Feldmann; Chirag Sudarshan; Christian Weis; Sven Oliver Krumke; Norbert Wehn (MEMSYS, 2020)

Efficient Hardware Architectures for 1D- and MD-LSTM Networks. - Vladimir Rybalkin; Chirag Sudarshan; Christian Weis; Jan Lappas; Norbert Wehn; Li Cheng (J. Signal Process. Syst., 2020)

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. - Dimitrios Stathis 001; Chirag Sudarshan; Yu Yang; Matthias Jung 001; Christian Weis; Ahmed Hemani; Anders Lansner; Norbert Wehn (J. Signal Process. Syst., 2020)

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. - Chirag Sudarshan; Taha Soliman; Cecilia De la Parra; Christian Weis; Leonardo Ecco; Matthias Jung 001; Norbert Wehn; Andre Guntoro (ASP-DAC, 2021)

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation. - Chirag Sudarshan; Lukas Steiner; Matthias Jung 001; Jan Lappas; Christian Weis; Norbert Wehn (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks. - Vladimir Rybalkin; Chirag Sudarshan; Christian Weis; Jan Lappas; Norbert Wehn; Li Cheng (J. Signal Process. Syst., 2021)

Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training. - Chirag Sudarshan; Mohammad Hassani Sadi; Christian Weis; Norbert Wehn (ISCAS, 2022)

A Framework for Formal Verification of DRAM Controllers. - Lukas Steiner; Chirag Sudarshan; Matthias Jung 001; Dominik Stoffel; Norbert Wehn (MEMSYS, 2022)

A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions. - Chirag Sudarshan; Mohammad Hassani Sadi; Lukas Steiner; Christian Weis; Norbert Wehn (SAMOS, 2022)

FeFET versus DRAM based PIM Architectures: A Comparative Study. - Chirag Sudarshan; Taha Soliman; Thomas Kämpfe; Christian Weis; Norbert Wehn (VLSI-SoC, 2022)

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. - Chirag Sudarshan; Taha Soliman; Jan Lappas; Christian Weis; Mohammad Hassani Sadi; Matthias Jung 001; Andre Guntoro; Norbert Wehn (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. - Gia Bao Thieu; Sven Gesper; Guillermo Payá-Vayá; Christoph Riggers; Oliver Renke; Till Fiedler; Jakob Marten; Tobias Stuckenberg; Holger Blume; Christian Weis; Lukas Steiner; Chirag Sudarshan; et al. (DATE, 2023)

Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories. - Paul-Philipp Manea; Chirag Sudarshan; Felix Cüppers; John Paul Strachan (NANOARCH, 2023)

Analog In-Memory Computing Attention Mechanism for Fast and Energy-Efficient Large Language Models. - Nathan Leroux; Paul-Philipp Manea; Chirag Sudarshan; Jan Finkbeiner; Sebastian Siegel; John Paul Strachan; Emre Neftci (CoRR, 2024)

Novel adaptive quantization methodology for 8-bit floating-point DNN training. - Mohammad Hassani Sadi; Chirag Sudarshan; Norbert Wehn (Des. Autom. Embed. Syst., 2024)