Interconnect Optimization Techniques in Data Path Synthesis. - Chittaranjan A. Mandal; Partha Pratim Chakrabarti; Sujoy Ghose (VLSI Design, 1992)

Register-interconnect optimization in data path synthesis. - Chittaranjan A. Mandal; P. P. Chakrabarti 001; Sujoy Ghose (Microprocess. Microprogramming, 1992)

Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach. - Chittaranjan A. Mandal; P. P. Chakrabarti 001; Sujoy Ghose (VLSI Design, 1996)

Design Space Exploration for Data Path Synthesis. - Chittaranjan A. Mandal; P. P. Chakrabarti 001; Sujoy Ghose (VLSI Design, 1997)

Complexity of Scheduling in High Level Synthesis. - Chittaranjan A. Mandal; Partha Pratim Chakrabarti; Sujoy Ghose (VLSI Design, 1998)

A design space exploration scheme for data-path synthesis. - Chittaranjan A. Mandal; P. P. Chakrabarti 001; Sujoy Ghose (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A Genetic Algorithm for the Synthesis of Structured Data Paths. - Chittaranjan A. Mandal; R. M. Zimmer (VLSI Design, 2000)

GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths. - Chittaranjan A. Mandal; P. P. Chakrabarti 001; Sujoy Ghose (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Timing analysis of tree-like RLC circuits. - Bipin Rajendran; Veerbhan Kheterpal; Abhishek Das; Jayanta Majumder; Chittaranjan A. Mandal; P. P. Chakrabarti 001 (ISCAS (4), 2002)

A New Approach to Timing Analysis Using Event Propagation and Temporal Logic. - Arijit Mondal; P. P. Chakrabarti 001; Chittaranjan A. Mandal (DATE, 2004)

High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count. - Soumya Pandit; Sougata Kar; Chittaranjan A. Mandal; Amit Patra (DATE, 2006)

A formal approach for high level synthesis of linear analog systems. - Soumya Pandit; Chittaranjan A. Mandal; Amit Patra (ACM Great Lakes Symposium on VLSI, 2006)

A Formal Verification Method of Scheduling in High-level Synthesis. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001; S. R. Pentakota; Chris Reade (ISQED, 2006)

Verification of Scheduling in High-level Synthesis. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001; S. R. Pentakota; Chris Reade (ISVLSI, 2006)

A System for Automatic Evaluation of Programs for Correctness and Performance. - Amit Kumar Mandal; Chittaranjan A. Mandal; Chris Reade (WEBIST (Selected Papers), 2006)

Animating Algorithms over the Web. - Chittaranjan A. Mandal; Chris Reade (WEBIST (2), 2006)

ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks. - Rajiv Misra; Chittaranjan A. Mandal (COMSWARE, 2007)

Hand-in-hand verification of high-level synthesis. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal; Chris Reade (ACM Great Lakes Symposium on VLSI, 2007)

Register Sharing Verification During Data-Path Synthesis. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001; Chris Reade (ICCTA, 2007)

Automatic Detection of Human Fall in Video. - Vinay Vishwakarma; Chittaranjan A. Mandal; Shamik Sural (PReMI, 2007)

Recipient Specific Electronic Cash - A Scheme for Recipient Specific Yet Anonymous and Tranferable Electronic Cash. - Chittaranjan A. Mandal; Chris Reade (WEBIST (3), 2007)

A System for Automatic Evaluation of C Programs: Features and Interfaces. - Amit Kumar Mandal; Chittaranjan A. Mandal; Chris Reade (Int. J. Web Based Learn. Teach. Technol., 2007)

An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. - Chandan Karfa; Dipankar Sarkar 001; Chitta Mandal; P. Kumar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Fast Exploration Procedure for Analog High-Level Specification Translation. - Soumya Pandit; Sumit K. Bhattacharya; Chittaranjan A. Mandal; Amit Patra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Location Updates of Mobile Node in Wireless Sensor Networks. - Rajiv Misra; Chittaranjan A. Mandal (MSN, 2009)

Systematic Methodology for High-Level Performance Modeling of Analog Systems. - Soumya Pandit; Chittaranjan A. Mandal; Amit Patra (VLSI Design, 2009)

Rotation of CDS via Connected Domatic Partition in Ad Hoc Sensor Networks. - Rajiv Misra; Chittaranjan A. Mandal (IEEE Trans. Mob. Comput., 2009)

Efficient clusterhead rotation via domatic partition in self-organizing sensor networks. - Rajiv Misra; Chittaranjan A. Mandal (Wirel. Commun. Mob. Comput., 2009)

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal (ISVLSI, 2010)

A BDD-Based Design of an Area-Power Efficient Asynchronous Adder. - Gopal Paul; Rohit Reddy; Chittaranjan A. Mandal; Bhargab B. Bhattacharya (ISVLSI, 2010)

A BDD-based approach to design power-aware on-line detectors for digital circuits. - Gopal Paul; Santosh Biswas; Chittaranjan A. Mandal; Bhargab B. Bhattacharya (SoCC, 2010)

An automated high-level topology generation procedure for continuous-time SigmaDelta modulator. - Soumya Pandit; Chittaranjan A. Mandal; Amit Patra (Integr., 2010)

Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. - Chandan Karfa; Dipankar Sarkar 001; Chitta Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Minimum Connected Dominating Set Using a Collaborative Cover Heuristic for Ad Hoc Sensor Networks. - Rajiv Misra; Chittaranjan A. Mandal (IEEE Trans. Parallel Distributed Syst., 2010)

POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads. - Priyankar Ghosh; Aritra Hazra; Niraj Bhilegaonkar; Pallab Dasgupta; Chittaranjan A. Mandal; Krishna Paul (ISED, 2011)

Equivalence Checking of Array-Intensive Programs. - Chandan Karfa; Kunal Banerjee 001; Dipankar Sarkar 001; Chitta Mandal (ISVLSI, 2011)

Verification of Register Transfer Level Low Power Transformations. - Chandan Karfa; Chitta Mandal; Dipankar Sarkar 001 (ISVLSI, 2011)

An improved greedy construction of minimum connected dominating sets in wireless networks. - Ariyam Das; Chittaranjan A. Mandal; Chris Reade; Manish Aasawat (WCNC, 2011)

A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. - Soumya Pandit; Chittaranjan A. Mandal; Amit Patra (VLSI Design, 2011)

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques. - Kunal Banerjee 001; Chandan Karfa; Dipankar Sarkar 001; Chittaranjan Mandal 001 (ISED, 2012)

Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker. - Soumyadip Bandyopadhyay; Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan A. Mandal (VDAT, 2012)

Workload Driven Power Domain Partitioning. - Arun Dobriyal; Rahul Gonnabattula; Pallab Dasgupta; Chittaranjan A. Mandal (VDAT, 2012)

A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. - Bapi Kar; Susmita Sur-Kolay; Sridhar H. Rangarajan; Chittaranjan A. Mandal (VDAT, 2012)

POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads. - Priyankar Ghosh; Aritra Hazra; Rahul Gonnabhaktula; Niraj Bhilegaonkar; Pallab Dasgupta; Chittaranjan A. Mandal; Krishna Paul (J. Low Power Electron., 2012)

Formal verification of code motion techniques using data-flow-driven equivalence checking. - Chandan Karfa; Chittaranjan A. Mandal; Dipankar Sarkar 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Determining the User Intent Behind Web Search Queries by Learning from Past User Interactions with Search Results. - Ariyam Das; Chittaranjan A. Mandal; Chris Reade (COMAD, 2013)

Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic. - Partha De; Kunal Banerjee 001; Chittaranjan A. Mandal; Debdeep Mukhopadhyay (DSD, 2013)

STAIRoute: Global routing using monotone staircase channels. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (ISVLSI, 2013)

Verification of KPN Level Transformations. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal (VLSI Design, 2013)

Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. - Chandan Karfa; Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan A. Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks. - Partha De; Kunal Banerjee 001; Chittaranjan A. Mandal; Debdeep Mukhopadhyay (DSD, 2014)

Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers. - Kunal Banerjee 001; Chittaranjan A. Mandal; Dipankar Sarkar 001 (VDAT, 2014)

A BDD based secure hardware design method to guard against power analysis attacks. - Partha De; Kunal Banerjee 001; Chittaranjan A. Mandal (VDAT, 2014)

Global Routing Using Monotone Staircases with Minimal Bends. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (VLSID, 2014)

Verification of Code Motion Techniques Using Value Propagation. - Kunal Banerjee 001; Chandan Karfa; Dipankar Sarkar 001; Chittaranjan A. Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs. - Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan A. Mandal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan A. Mandal (ICSE (2), 2015)

A Path-based Equivalence Checking Method for Petri Net based Models of Programs. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Kunal Banerjee 001; Chittaranjan A. Mandal (ICSOFT-EA, 2015)

Validating SPARK: High Level Synthesis Compiler. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan A. Mandal (ISVLSI, 2015)

Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking. - Kunal Banerjee 001; Chittaranjan A. Mandal; Dipankar Sarkar 001 (ISVLSI, 2015)

A New Method for Defining Monotone Staircases in VLSI Floorplans. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (ISVLSI, 2015)

Establishing Equivalence of Expressions: An Automated Evaluator Designer's Perspective. - K. K. Sharma; Kunal Banerjee 001; Chittaranjan A. Mandal (MIKE, 2015)

A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs. - Kunal Banerjee 001; Chittaranjan A. Mandal; Dipankar Sarkar 001 (SCAM, 2015)

Determining Equivalence of Expressions: An Automated Evaluator's Perspective. - K. K. Sharma; Kunal Banerjee 001; Chittaranjan A. Mandal (T4E, 2015)

An efficient path based equivalence checking for Petri net based models of programs. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan A. Mandal (ISEC, 2016)

Translation validation of loop and arithmetic transformations in the presence of recurrences. - Kunal Banerjee 001; Chittaranjan A. Mandal; Dipankar Sarkar 001 (LCTES, 2016)

An early global routing framework for uniform wire distribution in SoCs. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (SoCC, 2016)

A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (VLSID, 2016)

Construction of minimum connected dominating set in wireless sensor networks using pseudo dominating set. - Jasaswi Prasad Mohanty; Chittaranjan A. Mandal; Chris Reade; Ariyam Das (Ad Hoc Networks, 2016)

A Path Construction Algorithm for Translation Validation Using PRES+ Models. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan A. Mandal; Kunal Banerjee 001; Krishnam Raju Duddu (Parallel Process. Lett., 2016)

SamaTulyata: An Efficient Path Based Equivalence Checking Tool. - Soumyadip Bandyopadhyay; Santonu Sarkar; Dipankar Sarkar 001; Chittaranjan A. Mandal (ATVA, 2017)

An Equivalence Checking Framework for Array-Intensive Programs. - Kunal Banerjee 001; Chittaranjan A. Mandal; Dipankar Sarkar 001 (ATVA, 2017)

Distributed construction of minimum Connected Dominating Set in wireless sensor network using two-hop information. - Jasaswi Prasad Mohanty; Chittaranjan A. Mandal; Chris Reade (Comput. Networks, 2017)

Deriving bisimulation relations from path based equivalence checkers. - Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan A. Mandal (Formal Aspects Comput., 2017)

Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers. - Kunal Banerjee 001; Dipankar Sarkar 001; Chittaranjan Mandal 001 (IEEE Trans. Software Eng., 2017)

STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (CoRR, 2018)

Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (CoRR, 2018)

Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning. - Bapi Kar; Susmita Sur-Kolay; Chittaranjan A. Mandal (CoRR, 2018)

SamaTulyataOne: A Path Based Equivalence Checker. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan Mandal 001 (ISEC, 2019)

Equivalence checking of Petri net models of programs using static and dynamic cut-points. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan Mandal 001 (Acta Informatica, 2019)

Verification of parallelising transformations of KPN models. - Chandan Karfa; Dipankar Sarkar 001; Chittaranjan Mandal 001 (IET Cyper-Phys. Syst.: Theory & Appl., 2019)

Translation validation of coloured Petri net models of programs on integers. - Soumyadip Bandyopadhyay; Dipankar Sarkar 001; Chittaranjan A. Mandal; Holger Giese (Acta Informatica, 2022)