Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. - Chittarsu Raghunandan; K. S. Sainarayanan; M. B. Srinivas (ACM Great Lakes Symposium on VLSI, 2007)

Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN). - Chittarsu Raghunandan; K. S. Sainarayanan; M. B. Srinivas (ISCAS, 2007)

Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. - K. S. Sainarayanan; Chittarsu Raghunandan; M. B. Srinivas (ISVLSI, 2007)

Bus encoding schemes for minimizing delay in VLSI interconnects. - K. S. Sainarayanan; Chittarsu Raghunandan; M. B. Srinivas (SBCCI, 2007)

Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. - Chittarsu Raghunandan; K. S. Sainarayanan; M. B. Srinivas (ISQED, 2008)