A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application. - Qianqian Ha; Fan Ye 001; Chixiao Chen; Xiaoshi Zhu; Mingshuo Wang; Yu-Jing Lin; Ning Li 007; Junyan Ren (ASICON, 2011)

A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation. - Bei Yu; Chixiao Chen; Yu Zhu; Peng Zhang; Yiwen Zhang; Xiaoshi Zhu; Fan Ye 001; Junyan Ren (A-SSCC, 2011)

A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation. - Yiwen Zhang; Xiaoshi Zhu; Chixiao Chen; Fan Ye 001; Junyan Ren (APCCAS, 2012)

An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling. - Chixiao Chen; ShengChang Cai; Jialiang Xu; Xiaoshi Zhu; Fan Ye 001; Junyan Ren (MWSCAS, 2012)

A digitally calibrated current-steering DAC with current-splitting array. - Long Cheng; Chixiao Chen; Fan Ye 001; Ning Li 007; Junyan Ren (MWSCAS, 2012)

A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. - Yongzhen Chen; Chixiao Chen; Qiang Zhang; Fan Ye 001; Junyan Ren (ASICON, 2013)

A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator. - Zemin Feng; Chixiao Chen; Fan Ye 001; Jun Xu 011; Junyan Ren (ASICON, 2013)

A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers. - Yuzhong Xiao; Chixiao Chen; Rui Wei; Fan Jiang; Jun Xu 011; Junyan Ren (ASICON, 2013)

Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers. - Fan Jiang; Chixiao Chen; Yuzhong Xiao; Jun Xu 011; Junyan Ren (MWSCAS, 2013)

A mixed sample-time error calibration technique in time-interleaved ADCs. - Bei Yu; Chixiao Chen; Fan Ye 001; Junyan Ren (IEICE Electron. Express, 2013)

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1. - Zhenyu Wang; Mingshuo Wang; Weiru Gu; Chixiao Chen; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier. - Chixiao Chen; Zemin Feng; Huabin Chen; Mingshuo Wang; Jun Xu 011; Fan Ye 001; Junyan Ren (ISCAS, 2014)

A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. - Guoxian Dai; Chixiao Chen; Shunli Ma; Fan Ye 001; Junyan Ren (ISCAS, 2014)

A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method. - Zemin Feng; Jingjing Wang; Chixiao Chen; Jun Xu 011; Junyan Ren (ASICON, 2015)

100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. - Jingjing Wang; Rongjin Xu; Chixiao Chen; Fan Ye 001; Jun Xu 011; Junyan Ren (ASICON, 2015)

A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. - Shunli Ma; Guangyao Zhou; Jianbing Jiang; Chixiao Chen; Yongzhen Chen; Fan Ye 001; Junyan Ren (ESSCIRC, 2015)

A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators. - Chixiao Chen; Jixuan Xiang; Jiang Fan; Xu Jun; Ye Fan 001; Junyan Ren (IEICE Electron. Express, 2015)

An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators. - Chixiao Chen; Zemin Feng; Jun Xu 011; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network. - Bingwei Jiang; Chixiao Chen; Junyan Ren; Howard C. Luong (A-SSCC, 2016)

Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS. - Xiaolong Liu; Chixiao Chen; Junyan Ren; Howard C. Luong (A-SSCC, 2016)

OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators. - Chixiao Chen; Hongwei Ding; Huwan Peng; Haozhe Zhu; Rui Ma; Peiyong Zhang; Xiaolang Yan; Yu Wang 046; Mingyu Wang 001; Hao Min; Chuanjin Richard Shi (ESSCIRC, 2017)

High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators. - Hang Hu 003; Zemin Feng; Chixiao Chen; Fan Ye 001; Junyan Ren (MWSCAS, 2017)

Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing. - Aili Wang 002; Chixiao Chen; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Exploring the programmability for deep learning processors: from architecture to tensorization. - Chixiao Chen; Huwan Peng; Xindi Liu; Hongwei Ding; Chuanjin Richard Shi (DAC, 2018)

iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS. - Chixiao Chen; Xindi Liu; Huwan Peng; Hongwei Ding; Chuanjin Richard Shi (ESSCIRC, 2018)

OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators. - Chixiao Chen; Hongwei Ding; Huwan Peng; Haozhe Zhu; Yu Wang 046; Chuanjin Richard Shi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. - Liangjian Lyu; Yu Wang 046; Chixiao Chen; Chuanjin Richard Shi (ASP-DAC, 2019)

A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time. - Aili Wang 002; Chixiao Chen; Chuanjin Richard Shi (CICC, 2019)

A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. - Yongzhen Chen; Xingchen Shen; Zhekan Ni; Jingchao Lan; Chixiao Chen; Fan Ye 001; Junyan Ren (ESSCIRC, 2019)

Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. - Tianli Zhang; Yuefeng Cao; Shumin Zhang; Chixiao Chen; Fan Ye 001; Junyan Ren (ESSCIRC, 2019)

iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric. - Chixiao Chen; Xindi Liu; Huwan Peng; Hongwei Ding; Chuanjin Richard Shi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping. - Shiwei Liu 002; Haozhe Zhu; Chixiao Chen; Lihua Zhang; Chuanjin Richard Shi (AICAS, 2020)

A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network. - Min Chen 036; Yimin Wu; Jingchao Lan; Fan Ye 001; Chixiao Chen; Junyan Ren (APCCAS, 2020)

A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. - Haozhe Zhu; Chixiao Chen; Shiwei Liu 002; Qiaosha Zou; Mingyu Wang 001; Lihua Zhang; Xiaoyang Zeng; Chuanjin Richard Shi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. - Liangjian Lyu; Yu Wang 046; Chixiao Chen; Chuanjin Richard Shi (Integr., 2020)

Advances in Continuous-time MASH ΔΣ Modulators. - Liang Qi 002; Xinyu Qin; Sai-Weng Sin; Chixiao Chen; Fan Ye 001; Guoyong Shi; Guoxing Wang (ASICON, 2021)

A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA. - Bo Jiao; Jinshan Zhang 006; Yuanyuan Xie; Shunli Wang 001; Haozhe Zhu; Xiaoyang Kang 001; Zhiyan Dong; Lihua Zhang; Chixiao Chen (ASP-DAC, 2021)

Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors. - Bo Jiao; Haozhe Zhu; Jinshan Zhang 006; Shunli Wang 001; Xiaoyang Kang 001; Lihua Zhang; Mingyu Wang 001; Chixiao Chen (ACM Great Lakes Symposium on VLSI, 2021)

ALPINE: An Agile Processing-in-Memory Macro Compilation Framework. - Jinshan Zhang 006; Bo Jiao; Yunzhengmao Wang; Haozhe Zhu; Lihua Zhang; Chixiao Chen (ACM Great Lakes Symposium on VLSI, 2021)

Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. - Danfeng Zhai; Chixiao Chen; Liang Qi 002; Fan Ye 001; Junyan Ren (ISOCC, 2021)

Self-coupled MASH Delta-Sigma Modulator with Zero Optimization. - Jingying Zhang; Yang Zhao; Mingyi Chen; Chixiao Chen; Fan Ye 001; Liang Qi 002 (ISOCC, 2021)

TSA-Net: Tube Self-Attention Network for Action Quality Assessment. - Shunli Wang 001; Dingkang Yang; Peng Zhai; Chixiao Chen; Lihua Zhang (ACM Multimedia, 2021)

Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization. - Danfeng Zhai; Peizhe Li; Jiushan Zhang; Chixiao Chen; Fan Ye 001; Junyan Ren (MWSCAS, 2021)

A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. - Yuefeng Cao; Shumin Zhang; Tianli Zhang; Yongzhen Chen; Yutong Zhao; Chixiao Chen; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits. - Chen Mu; Yunzhengmao Wang; Jiapei Zheng; Shiwei Liu 002; Keji Zhou; Shan Tang; Chixiao Chen; Qi Liu 010 (AICAS, 2022)

Curriculum Adversarial Training for Robust Reinforcement Learning. - Junru Sheng; Peng Zhai; Zhiyan Dong; Xiaoyang Kang 001; Chixiao Chen; Lihua Zhang (IJCNN, 2022)

CA-SpaceNet: Counterfactual Analysis for 6D Pose Estimation in Space. - Shunli Wang 001; Shuaibing Wang; Bo Jiao; Dingkang Yang; Liuzhen Su; Peng Zhai; Chixiao Chen; Lihua Zhang (IROS, 2022)

A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization. - Xinru Jia; Haozhe Zhu; Yunzheng Wang; Jinshan Zhang 006; Feng Lin; Xiankui Xiong; Dong Xu 015; Chixiao Chen; Qi Liu 010 (ISCAS, 2022)

An Automated Compiler for RISC-V Based DNN Accelerator. - Zheng Wu; Wuzhen Xie; Xiaoling Yi; Haitao Yang; Ruiyao Pu; Xiankui Xiong; Haidong Yao; Chixiao Chen; Jun Tao 001; Fan Yang 001 (ISCAS, 2022)

NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models. - Xiaoling Yi; Jiangnan Yu; Zheng Wu; Xiankui Xiong; Dong Xu 015; Chixiao Chen; Jun Tao 001; Fan Yang 001 (ISCAS, 2022)

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. - Haozhe Zhu; Bo Jiao; Jinshan Zhang 006; Xinru Jia; Yunzhengmao Wang; Tianchan Guan; Shengcheng Wang; Dimin Niu; Hongzhong Zheng; Chixiao Chen; Mingyu Wang 001; Lihua Zhang; et al. (ISSCC, 2022)

Design Challenges of Intrachiplet and Interchiplet Interconnection. - Chixiao Chen; Jieming Yin; Yarui Peng; Maurizio Palesi; Wenxu Cao; Letian Huang; Amit Kumar Singh 002; Haocong Zhi; Xiaohang Wang 001 (IEEE Des. Test, 2022)

A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. - Keji Zhou; Xinru Jia; Chenyang Zhao 008; Xumeng Zhang; Guangjian Wu; Chen Mu; Haozhe Zhu; Yanting Ding; Chixiao Chen; Xiaoyong Xue; Xiaoyang Zeng; Qi Liu 010 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. - Danfeng Zhai; Wenning Jiang; Xinru Jia; Jingchao Lan; Mingqiang Guo; Sai-Weng Sin; Fan Ye 001; Qi Liu 010; Junyan Ren; Chixiao Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

2022 roadmap on neuromorphic devices and applications research in China. - Qing Wan; Changjin Wan; Huaqiang Wu; Yuchao Yang 001; Xiaohe Huang; Peng Zhou 021; Lin Chen; Tian-Yu Wang; Yi Li 049; Kanhao Xue; Yu-Hui He; Xiangshui Miao; et al. (Neuromorph. Comput. Eng., 2022)

Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation. - Siqi He; Hongyi Zhang; Mengjie Li; Haozhe Zhu; Chixiao Chen; Qi Liu 010; Xiaoyang Zeng (AICAS, 2023)

TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network. - Jiapei Zheng; Hao Jiang 024; Xinkai Nie; Zhangcheng Huang 001; Chixiao Chen; Qi Liu 010 (DAC, 2023)

TPNoC: An Efficient Topology Reconfigurable NoC Generator. - Jiangnan Yu; Fan Yang 001; Xiaoling Yi; Chixiao Chen; Jun Tao 001; Dong Xu 015; Xiankui Xiong; Haitao Yang (ACM Great Lakes Symposium on VLSI, 2023)

A $2.53 mu mathrm{W}/ text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. - Hao Jiang 024; Jiapei Zheng; Yunzhengmao Wang; Jinshan Zhang 006; Haozhe Zhu; Liangjian Lyu; Yingping Chen; Chixiao Chen; Qi Liu 010 (ISCAS, 2023)

A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. - Jie Liao; Bo Jiao; Jinshan Zhang 006; Shiwei Liu 002; Hao Jiang 024; Jun Tao 001; Wenning Jiang; Qi Liu 010; Lihua Zhang; Haozhe Zhu; Chixiao Chen (ISCAS, 2023)

A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier. - Xinsheng Wang; Maosong Shi; Peizhe Li; Jianwei Liu; Zhangcheng Huang 001; Chixiao Chen; Wenning Jiang (ISCAS, 2023)

A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. - Shiwei Liu 002; Peizhe Li; Jinshan Zhang 006; Yunzhengmao Wang; Haozhe Zhu; Wenning Jiang; Shan Tang; Chixiao Chen; Qi Liu 010; Ming Liu 022 (ISSCC, 2023)

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. - Wenning Jiang; Yan Zhu 001; Chixiao Chen; Hao Xu 005; Qi Liu 010; Ming Liu 022; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

A Real-Time Optical-Flow-based SLAM FPGA Accelerator with Inter-Frame Similarity Exploitation and Correlation-Guided Mixed-Precision Flow Update. - Mengjie Li; Haozhe Zhu; Yiming Zhang; Siqi He; Qi Liu 010; Xiaoyang Zeng; Chixiao Chen (A-SSCC, 2024)

A 28nm 76.25TOPS/W RRAM/SRAM-Collaborative CIM Fine-Tuning Accelerator with RRAM-Endurance/Latency-Aware Weight Allocation for CNN and Transformer. - Chen Mu; Zhirui Huang; Hao Jiang 024; Jie Liao; Bo Jiao; Yuliang Zhou; Haozhe Zhu; Jianguo Yang; Qi Liu 010; Chixiao Chen (A-SSCC, 2024)

ST-BPTT: A Memory-efficient BPTT SNN Training Approach through Gradient-Contribution-Driven Time-Step Selection. - Jiajun Lu; Haozhe Zhu; Xiaoyang Zeng; Chixiao Chen (BioCAS, 2024)

A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration. - Wenning Jiang; Yunbin Luo; Peizhe Li; Ji Guo; Chixiao Chen; Qi Liu 010 (CICC, 2024)

A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision. - Jingyi Wang; Zhangcheng Huang 001; Bu Chen; Hongyang Shang; Jiapei Zheng; Hankun Lv; Chixiao Chen; Qi Liu 010; Ming Liu 022 (CICC, 2024)

CEDAR: Computing-in-pixel Edge-aware Detection and Reconstruction Architecture for High-resolution 3D Imaging. - Bu Chen; Zhangcheng Huang 001; Qi Zheng 004; Weiyi Tang; Jingyi Wang; Hankun Lv; Chixiao Chen; Jianlu Wang; Qi Liu 010 (DAC, 2024)

CAMPER: Exploring the Potential of Content Addressable Memory for 3D Point Cloud Efficient Range Search. - Jiapei Zheng; Lizhou Wu; Yutong Su; Jingyi Wang; Zhangcheng Huang 001; Chixiao Chen; Qi Liu 010 (DAC, 2024)

ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test. - Hongyi Zhang; Haozhe Zhu; Siqi He; Mengjie Li; Chengchen Wang; Xiankui Xiong; Haidong Tian; Xiaoyang Zeng; Chixiao Chen (DATE, 2024)

A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder. - Mengjie Li; Hongyi Zhang; Siqi He; Haozhe Zhu; Hao Zhang; Jinglei Liu; Jiayuan Chen; Zhenping Hu; Xiaoyang Zeng; Chixiao Chen (ISCAS, 2024)

A 28-nm 10.4-fJ/b Cryogenic embedded DRAM with 3T1C Gain Cell and MBIST at 4-Kelvin. - Jiapei Zheng; Xinkai Nie; Zhenghang Zhi; Zhidong Tang; Qi Liu 010; Xufeng Kou; Chixiao Chen (ISOCC, 2024)

GauSPU: 3D Gaussian Splatting Processor for Real-Time SLAM Systems. - Lizhou Wu; Haozhe Zhu; Siqi He; Jiapei Zheng; Chixiao Chen; Xiaoyang Zeng (MICRO, 2024)

A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration. - Yinglin Yang; Yunzhengmao Wang; Tengyue Yi; Chixiao Chen; Qi Liu 010 (Integr., 2024)

HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. - Shiwei Liu 002; Chen Mu; Hao Jiang 024; Yunzhengmao Wang; Jinshan Zhang 006; Feng Lin; Keji Zhou; Qi Liu 010; Chixiao Chen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Trident-CIM: A LUT-Based Compute-in-Memory Macro With Trident Read Bit-Line and Partial Product Pruning. - Haozhe Zhu; Hongyi Zhang; Siqi He; Mengjie Li; Xiaoyang Zeng; Chixiao Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer. - Bo Jiao; Lei Xu; Xinyu Yu; Haitao Yang; Haozhe Zhu; Yu Wang; Jundong Zhu; Dexin Wen; Lingli Wang; Jun Tao 001; Chixiao Chen; Yinhe Han 001; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros. - Mengjie Li; Haozhe Zhu; Siqi He; Hongyi Zhang; Jie Liao; Danfeng Zhai; Chixiao Chen; Qi Liu 010; Xiaoyang Zeng; Ninghui Sun; Ming Liu 022 (IEEE J. Solid State Circuits, 2024)

Hi-NeRF: A Multicore NeRF Accelerator With Hierarchical Empty Space Skipping for Edge 3-D Rendering. - Lizhou Wu; Haozhe Zhu; Jiapei Zheng; Mengjie Li; Yinuo Cheng; Qi Liu 010; Xiaoyang Zeng; Chixiao Chen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

EIGEN: Enabling Efficient 3DIC Interconnect with Heterogeneous Dual-Layer Network-on-Active-Interposer. - Siyao Jia; Bo Jiao; Haozhe Zhu; Chixiao Chen; Qi Liu 010; Ming Liu 022 (HPCA, 2025)

A 0.22 pJ/bit Processing-in-Controller GEMV Macro with Weight Prefetch for Efficient Near-Memory Computing. - Jie Yang; Jiapei Zheng; Siqi He; Lizhou Wu; Chen Mu; Haozhe Zhu; Liyu Lin; Qi Liu 010; Chixiao Chen (ISCAS, 2025)

37.4 SHINSAI: A 586mm2 Reusable Active TSV Interposer with Programmable Interconnect Fabric and 512Mb 3D Underdeck Memory. - Bo Jiao; Haozhe Zhu; Yuman Zeng; Yongjiang Li; Jie Liao; Siyao Jia; Mochen Tian; Zexing Chen; Jundong Zhu; Dexin Wen; Yan Wang; Yu Wang 046; et al. (ISSCC, 2025)