A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. - Yan Li 084; Xu Cheng 002; Chiyu Tan; Jun Han 003; Yuanfu Zhao; Liang Wang 024; Tongde Li; Mehdi B. Tahoori; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. - Chiyu Tan; Yan Li 084; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)