Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. - Cho W. Moon; Paul R. Stephan; Robert K. Brayton (ICCAD, 1991)

Solving the State Assignment Problem for Signal Transition Graphs. - Luciano Lavagno; Cho W. Moon; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1992)

Sequential Circuit Design Using Synthesis and Optimization. - Ellen Sentovich; Kanwar Jit Singh; Cho W. Moon; Hamid Savoj; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1992)

Elimination of Dynamic hazards by Factoring. - Cho W. Moon; Robert K. Brayton (DAC, 1993)

Specification, synthesis, and verification of hazard-free asynchronous circuits. - Cho W. Moon; Paul R. Stephan; Robert K. Brayton (J. VLSI Signal Process., 1994)

An efficient heuristic procedure for solving the state assignment problem for event-based specifications. - Luciano Lavagno; Cho W. Moon; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Timing model extraction of hierarchical blocks by graph reduction. - Cho W. Moon; Harish Kriplani; Krishna P. Belkhale (DAC, 2002)