Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment. - Ranianand Venkata; Wilson Wong; Tina Tran; Vinson Chan; Tim Hoang; Henry Lui; Uinh Ton; Sergey Shomurryev; Chong Lee; Shoujun Waiig; Huy Ngo; Malik Kdhani; et al. (CICC, 2003)

Multi-protocol embedded PCS IP in a FPGA-SOC. - Ramanand Venkata; Vinson Chan; Binh Ton; Chong Lee; Huy Ngo; Malik Kabani; Tam Nguyen; Arch Zaliznyak; Ning Xue; Steven Shen; Michael Zheng; Michael Lai; et al. (CICC, 2005)