Graph Bipartization and via Minimization. - Hyeong-Ah Choi; Kazuo Nakajima; Chong S. Rim (SIAM J. Discret. Math., 1989)

Exact algorithms for multilayer topological via minimization. - Chong S. Rim; Toshinobu Kashiwabara; Kazuo Nakajima (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

General Circular Permutation Layout. - Ruey-Der Lou; Majid Sarrafzadeh; Chong S. Rim; Kazuo Nakajima; Sumio Masuda (Math. Syst. Theory, 1992)

Automatic Functional Cell Generation in the Sea-of-Gates Layout Style. - Yhonkyong Choi; Juhyun Lee; Chong S. Rim (ISCAS, 1994)

Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements. - Jagannathan Narasimham; Kazuo Nakajima; Chong S. Rim; Anton T. Dahbura (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

A Block Matching Algorithm with 16: 1 Subsampling and Its Hardware Design. - Yanghoon Kim; Chong S. Rim; Byoungki Min (ISCAS, 1995)

A simple and effective greedy multilayer router for MCMs. - Young-Jun Cha; Chong S. Rim; Kazuo Nakajima (ISPD, 1997)

Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards. - Yhonkyong Choi; Chong S. Rim (CICC, 1999)

A Graph Theoretical Approach for the Yield Enhancement of Reconfigurable VLSI/WSI Arrays. - Jagannathan Narasimhan; Kazuo Nakajima; Chong S. Rim (Discret. Appl. Math., 1999)

SEGRA: a very fast general area router for multichip modules. - Young-Jun Cha; Chong S. Rim; Kazuo Nakajima (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Adaptive Mixed Scheduling for Correcting Errors in Trapping Sets of LDPC Codes. - Saejoon Kim; Seunghyuk Lee; Jun Heo 002; Chong S. Rim (IEEE Commun. Lett., 2010)