Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation. - Shuyao Cheng; Chongxiao Li; Zidong Du; Rui Zhang 040; Xing Hu 001; Xiaqing Li; Guanglin Xu; Yuanbo Wen; Qi Guo 001 (DAC, 2024)

CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization. - Yang Zhao 013; Di Huang; Chongxiao Li; Pengwei Jin; Ziyuan Nan; TianYun Ma; Lei Qi; Yansong Pan; Zhenxing Zhang; Rui Zhang 040; Xishan Zhang; Zidong Du; et al. (CoRR, 2024)

AGON: Automated Design Framework for Customizing Processors from ISA Documents. - Chongxiao Li; Di Huang; Pengwei Jin; Tianyun Ma; Husheng Han; Shuyao Cheng; Yifan Hao 001; Yongwei Zhao; Guanglin Xu; Zidong Du; Rui Zhang 040; Xiaqing Li; et al. (CoRR, 2024)

QiMeng-CPU-v2: Automated Superscalar Processor Design by Learning Data Dependencies. - Shuyao Cheng; Rui Zhang 040; Wenkai He; Pengwei Jin; Chongxiao Li; Zidong Du; Xing Hu 001; Yifan Hao 001; Guanglin Xu; Yuanbo Wen; Ling Li 001; Qi Guo 001; et al. (CoRR, 2025)

CodeV-R1: Reasoning-Enhanced Verilog Generation. - Yaoyu Zhu; Di Huang; Han-Qi Lyu; Xiaoyun Zhang; Chongxiao Li; Wenxuan Shi; Yutong Wu; Jianan Mu; Jinghua Wang; Yang Zhao 013; Pengwei Jin; Shuyao Cheng; et al. (CoRR, 2025)

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs. - Pengwei Jin; Di Huang; Chongxiao Li; Shuyao Cheng; Yang Zhao 013; Xinyao Zheng; Jiaguo Zhu; Shuyi Xing; Bohan Dou; Rui Zhang 040; Zidong Du; Qi Guo 001; et al. (CoRR, 2025)