An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory. - Meng-Fan Chang; Shin-Jang Shen; Chia-Chi Liu; Che-Wei Wu; Yu-Fan Lin; Shang-Chi Wu; Chia-En Huang; Han-Chao Lai; Ya-Chin King; Chorng-Jung Lin; Hung-Jen Liao; Yu-Der Chih; et al. (ISSCC, 2011)

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time. - Meng-Fan Chang; Che-Wei Wu; Chia-Chen Kuo; Shin-Jang Shen; Ku-Feng Lin; Shu-Meng Yang; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih (ISSCC, 2012)

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory. - Meng-Fan Chang; Shin-Jang Shen; Chia-Chi Liu; Che-Wei Wu; Yu-Fan Lin; Ya-Chin King; Chorng-Jung Lin; Hung-Jen Liao; Yu-Der Chih; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2013)

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro. - Meng-Fan Chang; Che-Wei Wu; Chia-Chen Kuo; Shin-Jang Shen; Sue-Meng Yang; Ku-Feng Lin; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih (IEEE J. Solid State Circuits, 2013)

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Ku-Feng Lin; Yu-Der Chih; Sreedhar Natarajan; Tsung-Yung Jonathan Chang (ISSCC, 2014)

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme. - Meng-Fan Chang; Chia-Chen Kuo; Shyh-Shyuan Sheu; Chorng-Jung Lin; Ya-Chin King; Frederick T. Chen; Tzu-Kun Ku; Ming-Jinn Tsai; Jui-Jen Wu; Yu-Der Chih (IEEE J. Solid State Circuits, 2014)

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. - Wei-Hao Chen; Kai-Xiang Li; Wei-Yu Lin; Kuo-Hsiang Hsu; Pin-Yi Li; Cheng-Han Yang; Cheng-Xin Xue; En-Yu Yang; Yen-Kai Chen; Yun-Sheng Chang; Tzu-Hsiang Hsu; Ya-Chin King; et al. (ISSCC, 2018)

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors. - Cheng-Xin Xue; Wei-Hao Chen; Je-Syu Liu; Jia-Fang Li; Wei-Yu Lin; Wei-En Lin; Jing-Hong Wang; Wei-Chen Wei; Ting-Wei Chang; Tung-Cheng Chang; Tsung-Yuan Huang; Hui-Yao Kao; et al. (ISSCC, 2019)