A high-resolution and fast-conversion time-to-digital converter. - Chorng-Sii Hwang; Poki Chen; Hen-Wai Tsao (ISCAS (1), 2003)

A wide-range and fast-locking clock synthesizer IP based on delay-locked loop. - Chorng-Sii Hwang; Poki Chen; Hen-Wai Tsao (ISCAS (1), 2004)

A spread spectrum clock generator using digital modulation scheme. - Chorng-Sii Hwang; Huan-Chun Li; Hen-Wai Tsao (SoCC, 2008)

Dual-band CDR using a half-rate linear phase detector. - Chorng-Sii Hwang; Chun-Yung Cho; Chung-Chun Chen; Hen-Wai Tsao (SoCC, 2009)

Unambiguous BPSK-like CSC method for Galileo acquisition. - Wei-Lung Mao; Chorng-Sii Hwang; Chung-Wen Hung; Jyh Sheen; Po-Hung Chen (MMAR, 2013)

DLL-based programmable clock multiplier using differential toggle-pulsed latch. - Chorng-Sii Hwang; Ting-Li Chu; Po-Hsun Chen (SoCC, 2013)

A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction. - You-Gang Chen; Hen-Wai Tsao; Chorng-Sii Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability. - Ting-Li Chu; Sin-Hong Yu; Chorng-Sii Hwang (VLSI Design, 2013)

A clock generator based on multiplying delay-locked loop. - Chorng-Sii Hwang; Ting-Li Chu; Wen-Cheng Chen (SoCC, 2014)

An Area-Efficient CMOS Time-to-Digital Converter Based on a Pulse-Shrinking Scheme. - Chun-Chi Chen; Shih-Hao Lin; Chorng-Sii Hwang (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

All-digital deskew buffer using a hybrid control scheme. - Ting-Li Chu; Wen-Yu Chu; Yasuyoshi Fujii; Chorng-Sii Hwang (SoCC, 2015)

Corrigendum to "High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability". - Ting-Li Chu; Sin-Hong Yu; Chorng-Sii Hwang (VLSI Design, 2017)

All-Digital Cost-Efficient CMOS Digital-to-Time Converter Using Binary-Weighted Pulse Expansion. - Chun-Chi Chen; Chorng-Sii Hwang; Kai-Hsiang Chang (IEEE Trans. Very Large Scale Integr. Syst., 2020)