Design of low-power quaternary CMOS logic circuits. - Chotei Zukeran; Chushin Afuso; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1986)

Design of micropower CMOS quaternary memory circuits. - Chotei Zukeran; Chushin Afuso; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1987)

A State Assignment for p-Valued Sequential Machines. - Yasunori Nagata; Chotei Zukeran; Chushin Afuso (Syst. Comput. Jpn., 1990)

A universal literal circuit and its application to quaternary logic networks. - Chotei Zukeran; Yasunori Nagata; Chushin Afuso; Makoto Honda; Yutaka Nagamine (Syst. Comput. Jpn., 1992)

Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic Circuits. - Katsuhiko Shimabukuro; Chotei Zukeran (ISMVL, 1998)

Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. - Takahiro Hanyu; Michitaka Kameyama; Katsuhiko Shimabukuro; Chotei Zukeran (ISMVL, 2001)