Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM. - Yanwu Du; Chris Eom; Jake Jung; Brian Lee 003; Edwin Kim; Kanyu Cao (ASICON, 2021)

A 2-stage with 3-stack 1-tap DFE Sense Amplifier based on Dual Reference for High Speed & Low Power DRAM Interface. - Yinchuan Gu; Chris Eom; Jake Jung; Brian Lee 003; Edwin Kim; Kanyu Cao (ASICON, 2021)

Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector. - Siman Li; Chris Eom; Jake Jung; Brian Lee 003; Edwin Kim; Kanyu Cao (ASICON, 2021)

A Fast-Lock DLL with Prediction-Based Fast-Track FDL Structure for DDR5 SDRAMs. - Gaoyuan Pang; Brian Lee 003; Jake Jung; Chris Eom (ASICON, 2023)

A low power consumption and higher performance DDR5 receiver based on a direct feedback DFE and dedicated reference voltage for 1st TAP DFE. - Elaine Tang; Brian Lee 003; Chris Eom; Jake Jung (ASICON, 2023)

Pseudo differential DQS receiver for eliminating channel Hi-z noise. - Xueyan Zhang; Brian Lee 003; Chris Eom; Gaoyuan Pang; Jake Jung (ASICON, 2023)