Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. - Chris H. Kim; Kaushik Roy 001 (DATE, 2002)

Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. - Chris H. Kim; Kaushik Roy 001 (ISLPED, 2002)

A forward body-biased low-leakage SRAM cache: device and architecture considerations. - Chris H. Kim; Jae-Joon Kim; Saibal Mukhopadhyay; Kaushik Roy 001 (ISLPED, 2003)

Gate leakage reduction for scaled devices using transistor stacking. - Saibal Mukhopadhyay; Cassondra Neau; R. T. Cakici; Amit Agarwal 001; Chris H. Kim; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Leakage in nano-scale technologies: mechanisms, impact and design considerations. - Amit Agarwal 001; Chris H. Kim; Saibal Mukhopadhyay; Kaushik Roy 001 (DAC, 2004)

Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. - Hari Ananthan; Chris H. Kim; Kaushik Roy 001 (ISLPED, 2004)

Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling. - Ik Joon Chang; Kunhyuk Kang; Saibal Mukhopadhyay; Chris H. Kim; Kaushik Roy 001 (CICC, 2005)

Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. - Chris H. Kim; Steven Hsu; Ram Krishnamurthy 001; Shekhar Borkar; Kaushik Roy 001 (IOLTS, 2005)

Multi-story power delivery for supply noise reduction and low voltage operation. - Jie Gu 003; Chris H. Kim (ISLPED, 2005)

TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. - Keejong Kim; Chris H. Kim; Kaushik Roy 001 (ISQED, 2005)

A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. - Chris H. Kim; Jae-Joon Kim; Saibal Mukhopadhyay; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. - Sanjay V. Kumar; Chris H. Kim; Sachin S. Sapatnekar (ASP-DAC, 2006)

Width Quantization Aware FinFET Circuit Design. - Jie Gu 003; John Keane 001; Sachin S. Sapatnekar; Chris H. Kim (CICC, 2006)

Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. - John Keane 001; Hanyong Eom; Tony Tae-Hyoung Kim; Sachin S. Sapatnekar; Chris H. Kim (DAC, 2006)

An analytical model for negative bias temperature instability. - Sanjay V. Kumar; Chris H. Kim; Sachin S. Sapatnekar (ICCAD, 2006)

Modeling and analysis of leakage induced damping effect in low voltage LSIs. - Jie Gu 003; John Keane 001; Chris H. Kim (ISLPED, 2006)

Impact of NBTI on SRAM Read Stability and Design for Reliability. - Sanjay V. Kumar; Chris H. Kim; Sachin S. Sapatnekar (ISQED, 2006)

Leakage Power Analysis and Reduction for Nanoscale Circuits. - Amit Agarwal 001; Saibal Mukhopadhyay; Arijit Raychowdhury; Kaushik Roy 001; Chris H. Kim (IEEE Micro, 2006)

A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. - Chris H. Kim; Kaushik Roy 001; Steven Hsu; Ram Krishnamurthy 001; Shekhar Borkar (IEEE Trans. Very Large Scale Integr. Syst., 2006)

An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement. - Tony Tae-Hyoung Kim; Jason Liu 004; Chris H. Kim (CICC, 2007)

Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. - Jie Gu 003; Sachin S. Sapatnekar; Chris H. Kim (DAC, 2007)

NBTI-Aware Synthesis of Digital Circuits. - Sanjay V. Kumar; Chris H. Kim; Sachin S. Sapatnekar (DAC, 2007)

Modeling and estimating leakage current in series-parallel CMOS networks. - Paulo F. Butzen; André Inácio Reis; Chris H. Kim; Renato P. Ribas (ACM Great Lakes Symposium on VLSI, 2007)

Sleep transistor sizing and control for resonant supply noise damping. - Jie Gu 003; Hanyong Eom; Chris H. Kim (ISLPED, 2007)

A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme. - Tony Tae-Hyoung Kim; Jason Liu 004; John Keane 001; Chris H. Kim (ISSCC, 2007)

Modeling Subthreshold Leakage Current in General Transistor Networks. - Paulo F. Butzen; André Inácio Reis; Chris H. Kim; Renato P. Ribas (ISVLSI, 2007)

Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. - Paulo F. Butzen; André Inácio Reis; Chris H. Kim; Renato P. Ribas (PATMOS, 2007)

Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors. - Hiroaki Suzuki; Chris H. Kim; Kaushik Roy 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. - Tony Tae-Hyoung Kim; John Keane 001; Hanyong Eom; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode. - Tony Tae-Hyoung Kim; Jason Liu 004; Chris H. Kim (CICC, 2008)

Circuit techniques for ultra-low power subthreshold SRAMs. - Tony Tae-Hyoung Kim; Jason Liu 004; John Keane 001; Chris H. Kim (ISCAS, 2008)

A multi-story power delivery technique for 3D integrated circuits. - Pulkit Jain; Tony Tae-Hyoung Kim; John Keane 001; Chris H. Kim (ISLPED, 2008)

Enhancing beneficial jitter using phase-shifted clock distribution. - Dong Jiao; Jie Gu 003; Pulkit Jain; Chris H. Kim (ISLPED, 2008)

Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies. - Chris H. Kim (ISQED, 2008)

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing. - Tony Tae-Hyoung Kim; Jason Liu 004; John Keane 001; Chris H. Kim (IEEE J. Solid State Circuits, 2008)

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits. - Tony Tae-Hyoung Kim; Randy Persaud; Chris H. Kim (IEEE J. Solid State Circuits, 2008)

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. - Jie Gu 003; John Keane 001; Sachin S. Sapatnekar; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. - John Keane 001; Hanyong Eom; Tony Tae-Hyoung Kim; Sachin S. Sapatnekar; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting. - Jonggab Kil; Jie Gu 003; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Body Bias Voltage Computations for Process and Temperature Compensation. - Sanjay V. Kumar; Chris H. Kim; Sachin S. Sapatnekar (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Adaptive techniques for overcoming performance degradation due to aging in digital circuits. - Sanjay V. Kumar; Chris H. Kim; Sachin S. Sapatnekar (ASP-DAC, 2009)

Circuit techniques for enhancing the clock data compensation effect under resonant supply noise. - Dong Jiao; Jie Gu 003; Chris H. Kim (CICC, 2009)

An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation. - Tony Tae-Hyoung Kim; Wei Zhang 032; Chris H. Kim (CICC, 2009)

A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. - Ki Chul Chun; Pulkit Jain; Chris H. Kim (ISLPED, 2009)

On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit. - Jie Gu 003; Hanyong Eom; Chris H. Kim (IEEE J. Solid State Circuits, 2009)

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode. - Tony Tae-Hyoung Kim; Jason Liu 004; Chris H. Kim (IEEE J. Solid State Circuits, 2009)

Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance. - Jie Gu 003; Hanyong Eom; John Keane 001; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs. - Jie Gu 003; Ramesh Harjani; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity. - Jie Gu 003; John Keane 001; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Logic-compatible embedded DRAM design for memory intensive low power systems. - Ki Chul Chun; Pulkit Jain; Chris H. Kim (ISCAS, 2010)

Variation aware performance analysis of gain cell embedded DRAMs. - Wei Zhang 032; Ki Chul Chun; Chris H. Kim (ISLPED, 2010)

Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise. - Dong Jiao; Jie Gu 003; Chris H. Kim (IEEE J. Solid State Circuits, 2010)

An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB. - John Keane 001; Xiaofei Wang; Devin Persaud; Chris H. Kim (IEEE J. Solid State Circuits, 2010)

On-chip reliability monitors for measuring circuit degradation. - John Keane 001; Tony Tae-Hyoung Kim; Xiaofei Wang; Chris H. Kim (Microelectron. Reliab., 2010)

An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation. - John Keane 001; Tony Tae-Hyoung Kim; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network. - Pingqiang Zhou; Dong Jiao; Chris H. Kim; Sachin S. Sapatnekar (CICC, 2011)

A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies. - Ki Chul Chun; Wei Zhang 032; Pulkit Jain; Chris H. Kim (ISSCC, 2011)

A programmable adaptive phase-shifting PLL for clock data compensation under resonant supply noise. - Dong Jiao; Chris H. Kim (ISSCC, 2011)

A 1V printed organic DRAM cell based on ion-gel gated transistors with a sub-10nW-per-cell Refresh Power. - Wei Zhang 032; Mingjing Ha; Daniele Braga; Michael J. Renn; C. Daniel Frisbie; Chris H. Kim (ISSCC, 2011)

Guest editors' introduction: Nanoscale Memories Pose Unique Challenges. - Chris H. Kim; Leland Chang (IEEE Des. Test Comput., 2011)

A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches. - Ki Chul Chun; Pulkit Jain; Jung-Hwa Lee; Chris H. Kim (IEEE J. Solid State Circuits, 2011)

An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization. - John Keane 001; Wei Zhang 032; Chris H. Kim (IEEE J. Solid State Circuits, 2011)

An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. - John Keane 001; Shrinivas Venkatraman; Paulo F. Butzen; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. - Sanjay V. Kumar; Chris H. Kim; Sachin S. Sapatnekar (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. - Ayan Paul; Matt Amrein; Saket Gupta; Arvind Vinod; Abhishek Arun; Sachin S. Sapatnekar; Chris H. Kim (CICC, 2012)

An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs. - Pulkit Jain; John Keane 001; Chris H. Kim (ESSDERC, 2012)

Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. - Pingqiang Zhou; Won Ho Choi; Bongjin Kim; Chris H. Kim; Sachin S. Sapatnekar (ICCAD, 2012)

Design of ring oscillator structures for measuring isolated NBTI and PBTI. - Tony T. Kim; Pong-Fei Lu; Chris H. Kim (ISCAS, 2012)

A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme. - Seung-Hwan Song; Ki Chul Chun; Chris H. Kim (VLSIC, 2012)

Process and Reliability Sensors for Nanoscale CMOS. - John Keane 001; Chris H. Kim; Qunzeng Liu; Sachin S. Sapatnekar (IEEE Des. Test Comput., 2012)

A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor. - Ki Chul Chun; Wei Zhang 032; Pulkit Jain; Chris H. Kim (IEEE J. Solid State Circuits, 2012)

A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches. - Ki Chul Chun; Pulkit Jain; Tae-Ho Kim; Chris H. Kim (IEEE J. Solid State Circuits, 2012)

Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation. - Dong Jiao; Bongjin Kim; Chris H. Kim (IEEE J. Solid State Circuits, 2012)

An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of VMIN Degradation. - Tony Tae-Hyoung Kim; Wei Zhang 032; Chris H. Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal. - Bongjin Kim; Weichao Xu; Chris H. Kim (CICC, 2013)

A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications. - Seung-Hwan Song; Ki Chul Chun; Chris H. Kim (CICC, 2013)

A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory. - Ki Chul Chun; Hui Zhao; Jonathan D. Harms; Tony Tae-Hyoung Kim; Jianping Wang 006; Chris H. Kim (IEEE J. Solid State Circuits, 2013)

A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme. - Seung-Hwan Song; Ki Chul Chun; Chris H. Kim (IEEE J. Solid State Circuits, 2013)

A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode. - Wei Zhang 032; Ki Chul Chun; Chris H. Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage. - Won Ho Choi; Saroj Satapathy; John Keane 001; Chris H. Kim (CICC, 2014)

A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals. - Bongjin Kim; Somnath Kundu; Seokkyun Ko; Chris H. Kim (CICC, 2014)

True Random Number Generator circuits based on single- and multi-phase beat frequency detection. - Qianying Tang; Bongjin Kim; Yingjie Lao; Keshab K. Parhi; Chris H. Kim (CICC, 2014)

SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data. - Xiaofei Wang; Weichao Xu; Chris H. Kim (CICC, 2014)

Improving STT-MRAM density through multibit error correction. - Brandon Del Bel; Jongyeon Kim; Chris H. Kim; Sachin S. Sapatnekar (DATE, 2014)

Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. - Ayan Paul; Chaitanya Kshirsagar; Sachin S. Sapatnekar; Steven J. Koester; Chris H. Kim (VLSID, 2014)

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter. - Bongjin Kim; Weichao Xu; Chris H. Kim (IEEE J. Solid State Circuits, 2014)

A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications. - Seung-Hwan Song; Ki Chul Chun; Chris H. Kim (IEEE J. Solid State Circuits, 2014)

Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design. - Xiaofei Wang; John Keane 001; Tony Tae-Hyoung Kim; Pulkit Jain; Qianying Tang; Chris H. Kim (IEEE Micro, 2014)

Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems. - Pingqiang Zhou; Ayan Paul; Chris H. Kim; Sachin S. Sapatnekar (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs. - Won Ho Choi; Hoon Ki Kim; Chris H. Kim (CICC, 2015)

A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies. - Jongyeon Kim; An Chen; Behtash Behin-Aein; Saurabh Kumar 003; Jianping Wang 006; Chris H. Kim (CICC, 2015)

An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier. - Bongjin Kim; Hoon Ki Kim; Chris H. Kim (CICC, 2015)

Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals. - Somnath Kundu; Bongjin Kim; Chris H. Kim (CICC, 2015)

A revolving reference odometer circuit for BTI-induced frequency fluctuation measurements under fast DVFS transients. - Saroj Satapathy; Won Ho Choi; Xiaofei Wang; Chris H. Kim (IRPS, 2015)

Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR). - Rahul Parhi; Chris H. Kim; Keshab K. Parhi (ISCAS, 2015)

A 8-14 GHz varactorless current controlled LC oscillator in 16nm CMOS technology. - Somnath Kundu; Vassili Kireev; Chris H. Kim (MWSCAS, 2015)

A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit. - Bongjin Kim; Somnath Kundu; Chris H. Kim (VLSIC, 2015)

Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor. - Jongyeon Kim; Ayan Paul; Paul A. Crowell; Steven J. Koester; Sachin S. Sapatnekar; Jianping Wang 006; Chris H. Kim (Proc. IEEE, 2015)

A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology. - Tony Tae-Hyoung Kim; Pong-Fei Lu; Keith A. Jenkins; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications. - Xiaofei Wang; Qianying Tang; Pulkit Jain; Dong Jiao; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Estimating delay differences of arbiter PUFs using silicon data. - S. V. Sandeep Avvaru; Chen Zhou; Saroj Satapathy; Yingjie Lao; Chris H. Kim; Keshab K. Parhi (DATE, 2016)

Mode-based Obfuscation using Control-Flow Modifications. - Sandhya Koteshwara; Chris H. Kim; Keshab K. Parhi (CS2@HiPEAC, 2016)

Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs. - Chen Zhou; Saroj Satapathy; Yingjie Lao; Keshab K. Parhi; Chris H. Kim (ISLPED, 2016)

19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection. - Somnath Kundu; Bongjin Kim; Chris H. Kim (ISSCC, 2016)

CoMET: Composite-Input Magnetoelectric-based Logic Technology. - Meghna G. Mankalale; Zhaoxin Liang; Zhengyang Zhao 001; Chris H. Kim; Jianping Wang 006; Sachin S. Sapatnekar (CoRR, 2016)

Beat Frequency Detector-Based High-Speed True Random Number Generators: Statistical Modeling and Analysis. - Yingjie Lao; Qianying Tang; Chris H. Kim; Keshab K. Parhi (ACM J. Emerg. Technol. Comput. Syst., 2016)

A 0.0054-mm2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor. - Somnath Kundu; Chris H. Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators. - Ayan Paul; Sang Phill Park; Dinesh Somasekhar; Young Moon Kim; Nitin Borkar; Ulya R. Karpuzcu; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Functional encryption of integrated circuits by key-based hybrid obfuscation. - Sandhya Koteshwara; Chris H. Kim; Keshab K. Parhi (ACSSC, 2017)

A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities. - Muqing Liu; Luke R. Everson; Chris H. Kim (CICC, 2017)

A DRAM based physical unclonable function capable of generating >1032 Challenge Response Pairs per 1Kbit array for secure chip authentication. - Qianying Tang; Chen Zhou; Woong Choi; Gyuseong Kang; Jongsun Park 001; Keshab K. Parhi; Chris H. Kim (CICC, 2017)

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. - Jianping Wang 006; Sachin S. Sapatnekar; Chris H. Kim; Paul A. Crowell; Steven J. Koester; Supriyo Datta; Kaushik Roy 001; Anand Raghunathan; Xiaobo Sharon Hu; Michael T. Niemier; Azad Naeemi; Chia-Ling Chien; et al. (DAC, 2017)

Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements. - Chen Zhou; Keshab K. Parhi; Chris H. Kim (DAC, 2017)

Advanced spintronic memory and logic for non-volatile processors. - Robert Perricone; Ibrahim Ahmed 002; Zhaoxin Liang; Meghna G. Mankalale; Xiaobo Sharon Hu; Chris H. Kim; Michael T. Niemier; Sachin S. Sapatnekar; Jianping Wang 006 (DATE, 2017)

Hierarchical functional obfuscation of integratec circuits using a mode-based approach. - Sandhya Koteshwara; Chris H. Kim; Keshab K. Parhi (ISCAS, 2017)

An entropy test for determining whether a MUX PUF is linear or nonlinear. - Anoop Koyily; Chen Zhou; Chris H. Kim; Keshab K. Parhi (ISCAS, 2017)

A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology. - Somnath Kundu; Chris H. Kim (ISCAS, 2017)

A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function. - Muqing Liu; Chen Zhou; Qianying Tang; Keshab K. Parhi; Chris H. Kim (ISLPED, 2017)

Predicting hard and soft-responses and identifying stable challenges of MUX PUFs using ANNs. - S. V. Sandeep Avvaru; Chen Zhou; Chris H. Kim; Keshab K. Parhi (MWSCAS, 2017)

A Non-volatile Near-Memory Read Mapping Accelerator. - S. Karen Khatamifard; Zamshed I. Chowdhury; Nakul Pande; Meisam Razaviyayn; Chris H. Kim; Ulya R. Karpuzcu (CoRR, 2017)

R-DBN: A Resistive Deep Belief Network Architecture Leveraging the Intrinsic Behavior of Probabilistic Devices. - Ramtin Zand; Kerem Yunus Çamsari; Ibrahim Ahmed 002; Steven D. Pyle; Chris H. Kim; Supriyo Datta; Ronald F. DeMara (CoRR, 2017)

A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection. - Somnath Kundu; Bongjin Kim; Chris H. Kim (IEEE J. Solid State Circuits, 2017)

Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit. - Qianying Tang; Chris H. Kim (IEEE J. Solid State Circuits, 2017)

Reliable PUF-Based Local Authentication With Self-Correction. - Yingjie Lao; Bo Yuan 001; Chris H. Kim; Keshab K. Parhi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Effect of aging on linear and nonlinear MUX PUFs by statistical modeling. - Anoop Koyily; Satya Venkata Sandeep Avvaru; Chen Zhou; Chris H. Kim; Keshab K. Parhi (ASP-DAC, 2018)

A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. - Po-Wei Chiu; Muqing Liu; Qianying Tang; Chris H. Kim (A-SSCC, 2018)

A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm. - Luke R. Everson; Muqing Liu; Nakul Pande; Chris H. Kim (A-SSCC, 2018)

A 0.0094mm2/Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording. - Luke R. Everson; Somnath Kundu; Gang Chen; Zhi Yang; Timothy J. Ebner; Chris H. Kim (BioCAS, 2018)

Low-Energy Deep Belief Networks Using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons. - Ramtin Zand; Kerem Yunus Çamsari; Steven D. Pyle; Ibrahim Ahmed 002; Chris H. Kim; Ronald F. DeMara (ACM Great Lakes Symposium on VLSI, 2018)

All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. - Gyusung Park; Minsu Kim; Chris H. Kim; Bongjin Kim; Vijay Reddy (IRPS, 2018)

BiometricNet: Deep Learning based Biometric Identification using Wrist-Worn PPG. - Luke R. Everson; Dwaipayan Biswas; Madhuri Panwar; Dimitrios Rodopoulos; Amit Acharyya; Chris H. Kim; Chris Van Hoof; Mario Konijnenburg; Nick Van Helleputte (ISCAS, 2018)

Predicting Soft-Response of MUX PUFs via Logistic Regression of Total Delay Difference. - Anoop Koyily; Chen Zhou; Chris H. Kim; Keshab K. Parhi (ISCAS, 2018)

A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC. - Qianying Tang; Won Ho Choi; Luke R. Everson; Keshab K. Parhi; Chris H. Kim (ISCAS, 2018)

A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning. - Somnath Kundu; Muqing Liu; Richard Wong; Shi-Jie Wen; Chris H. Kim (ISSCC, 2018)

A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer. - Po-Wei Chiu; Somnath Kundu; Qianying Tang; Chris H. Kim (IEEE J. Solid State Circuits, 2018)

Key-Based Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered Mode-Based Design. - Sandhya Koteshwara; Chris H. Kim; Keshab K. Parhi (IEEE Trans. Inf. Forensics Secur., 2018)

Real-time HR Estimation from wrist PPG using Binary LSTMs. - Leandro Mateus Giacomini Rocha; Nick Van Helleputte; Muqing Liu; Dwaipayan Biswas; Bram-Ernst Verhoef; Sergio Bampi; Chris H. Kim; Chris Van Hoof; Mario Konijnenburg; Marian Verhelst (BioCAS, 2019)

A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing. - Gyusung Park; Minsu Kim; Nakul Pande; Po-Wei Chiu; Jeehwan Song; Chris H. Kim (CICC, 2019)

BioTranslator: Inferring R-Peaks from Ambulatory Wrist-Worn PPG Signal. - Luke R. Everson; Dwaipayan Biswas; Bram-Ernst Verhoef; Chris H. Kim; Chris Van Hoof; Mario Konijnenburg; Nick Van Helleputte (EMBC, 2019)

Investigating the Aging Dynamics of Diode-Connected MOS Devices Using an Array-Based Characterization Vehicle in a 65nm Process. - Nakul Pande; Gyusung Park; Chris H. Kim; Srikanth Krishnan; Vijay Reddy (IRPS, 2019)

A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control. - Luke R. Everson; Sachin S. Sapatnekar; Chris H. Kim (ISSCC, 2019)

An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm. - Luke R. Everson; Muqing Liu; Nakul Pande; Chris H. Kim (IEEE J. Solid State Circuits, 2019)

A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer. - Somnath Kundu; Muqing Liu; Shi-Jie Wen; Richard Wong; Chris H. Kim (IEEE J. Solid State Circuits, 2019)

CorNET: Deep Learning Framework for PPG-Based Heart Rate Estimation and Biometric Identification in Ambulant Environment. - Dwaipayan Biswas; Luke R. Everson; Muqing Liu; Madhuri Panwar; Bram-Ernst Verhoef; Shrishail Patki; Chris H. Kim; Amit Acharyya; Chris Van Hoof; Mario Konijnenburg; Nick Van Helleputte (IEEE Trans. Biomed. Circuits Syst., 2019)

Reliability Characterization of Logic-Compatible NAND Flash Memory based Synapses with 3-bit per Cell Weights and 1μA Current Steps. - Minsu Kim; Jeehwan Song; Chris H. Kim (IRPS, 2020)

22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor. - Po-Wei Chiu; Chris H. Kim (ISSCC, 2020)

A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. - Ibrahim Ahmed 002; Po-Wei Chiu; Chris H. Kim (VLSI Circuits, 2020)

Extreme Temperature Characterization of Amplifier Response up to 300 Degrees Celsius Using Integrated Heaters and On-chip Samplers. - Hanzhao Yu; Gyusung Park; Chris H. Kim (ESSCIRC, 2021)

An All BTI (N-PBTI, N-NBTI, P-PBTI, P-NBTI) Odometer based on a Dual Power Rail Ring Oscillator Array. - Gyusung Park; Hanzhao Yu; Minsu Kim; Chris H. Kim (IRPS, 2021)

A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. - Ibrahim Ahmed 002; Po-Wei Chiu; William Moy; Chris H. Kim (IEEE J. Solid State Circuits, 2021)

A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control. - Luke R. Everson; Sachin S. Sapatnekar; Chris H. Kim (IEEE J. Solid State Circuits, 2021)

A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. - Saurabh Kumar 003; Minki Cho; Luke R. Everson; Andres Malavasi; Dan Lake; Carlos Tokunaga; Muhammad M. Khellah; James W. Tschanz; Vivek De; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. - Sriram R. Vangal; Somnath Paul; Steven Hsu; Amit Agarwal 001; Saurabh Kumar 003; Ram Krishnamurthy 001; Harish Krishnamurthy; James W. Tschanz; Vivek De; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Calibration-Free Synthesizable Odometer Featuring Automatic Frequency Dead Zone Escape and Start-up Glitch Removal. - Tahmida Islam; Junkyu Kim; Chris H. Kim; David Tipple; Michael Nelson; Robert Jin; Anis Jarrar (IRPS, 2022)

Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation (Invited). - Armen Kteyan; Valeriy Sukharev; Y. Yi; Chris H. Kim (IRPS, 2022)

An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process. - Minsu Kim; Muqing Liu; Luke R. Everson; Chris H. Kim (IEEE J. Solid State Circuits, 2022)

Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids. - Valeriy Sukharev; Armen Kteyan; Farid N. Najm; Yong Hyeon Yi; Chris H. Kim; Jun-Ho Choy; Sofya Torosyan; Yu Zhu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors. - Po-Wei Chiu; Chris H. Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

GeNVoM: Read Mapping Near Non-Volatile Memory. - S. Karen Khatamifard; Zamshed I. Chowdhury; Nakul Pande; Meisam Razaviyayn; Chris H. Kim; Ulya R. Karpuzcu (IEEE ACM Trans. Comput. Biol. Bioinform., 2022)

Studying the Impact of Temperature Gradient on Electromigration Lifetime Using a Power Grid Test Structure with On-Chip Heaters. - Yong Hyeon Yi; Chris H. Kim; Chen Zhou; Armen Kteyan; Valeriy Sukharev (IRPS, 2023)

Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution. - Armen Kteyan; Valeriy Sukharev; Alexander Volkov; Jun-Ho Choy; Farid N. Najm; Yong Hyeon Yi; Chris H. Kim; Stéphane Moreau (ISPD, 2023)

3SAT on an All-to-All-Connected CMOS Ising Solver Chip. - M. Hüsrev Cilasun; Ziqing Zeng; Ramprasath S 001; Abhimanyu Kumar; Hao Lo; William Cho; Chris H. Kim; Ulya R. Karpuzcu; Sachin S. Sapatnekar (CoRR, 2023)

Quantum-Inspired Machine Learning Framework using a Physics-based Ising Solver Chip. - Ameya Khot; Taesic Kim; Alve Rahman Akash; Chris H. Kim; William Moy (ICPS, 2024)

Electromigration Test Chip Experiments from Realistic Power Grid Structures: Failure Trend Comparison and Statistical Analysis. - Yong Hyeon Yi; Chris H. Kim; Armen Kteyan; Alexander Volkov; Stéphane Moreau; Valeriy Sukharev (IRPS, 2024)

COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization. - Hüsrev Cilasun; William Moy; Ziqing Zeng; Tahmida Islam; Hao Lo; Alex Vanasse; Megan Tan; Mohammad Anees; Ramprasath S 001; Abhimanyu Kumar; Sachin S. Sapatnekar; Chris H. Kim; et al. (Zenodo, 2024)

Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design. - Xiaoxuan Yang 001; Zhangyang Wang; X. Sharon Hu; Chris H. Kim; Shimeng Yu; Miroslav Pajic; Rajit Manohar; Yiran Chen 001; Hai Helen Li (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Tracking Fmax Degradation of a RISC-V CPU with Synthesizable Odometer Aging Sensors. - Tahmida Islam; Junkyu Kim; Hanzhao Yu; Chris H. Kim (CICC, 2025)

Aging Characterization at Cryogenic Temperature with Synthesizable Odometers in 12NM and 28NM. - Tahmida Islam; Junkyu Kim; Hanzhao Yu; Zheng Xue; Jacob Xing; Chris H. Kim; Jiesi Xing; Christopher Elash; Peiman Pour Momen; Li Chen (IRPS, 2025)

DROID: Discrete-Time Simulation for Ring-Oscillator-Based Ising Design. - Abhimanyu Kumar; S. Ramprasath 001; Chris H. Kim; Ulya R. Karpuzcu; Sachin S. Sapatnekar (CoRR, 2025)