Using Hard Macros to Reduce FPGA Compilation Time. - Christopher Lavin; Marc Padilla; Subhrashankha Ghosh; Brent E. Nelson; Brad L. Hutchings; Michael J. Wirthlin (FPL, 2010)

Rapid prototyping tools for FPGA designs: RapidSmith. - Christopher Lavin; Marc Padilla; Philip Lundrigan; Brent E. Nelson; Brad L. Hutchings (FPT, 2010)

HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping. - Christopher Lavin; Marc Padilla; Jaren Lamprecht; Philip Lundrigan; Brent E. Nelson; Brad L. Hutchings (FCCM, 2011)

RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. - Christopher Lavin; Marc Padilla; Jaren Lamprecht; Philip Lundrigan; Brent E. Nelson; Brad L. Hutchings (FPL, 2011)

Impact of hard macro size on FPGA clock rate and place/route time. - Christopher Lavin; Brent E. Nelson; Brad L. Hutchings (FPL, 2013)

Improving clock-rate of hard-macro designs. - Christopher Lavin; Brent E. Nelson; Brad L. Hutchings (FPT, 2013)

Space-Time Coding for Aeronautical Telemetry: Part II - Decoder and System Performance. - Michael Rice; Tom Nelson; Joseph M. Palmer; Christopher Lavin; Kip Temple (IEEE Trans. Aerosp. Electron. Syst., 2017)

Space-Time Coding for Aeronautical Telemetry: Part I - Estimators. - Michael Rice; Joseph M. Palmer; Christopher Lavin; Tom Nelson (IEEE Trans. Aerosp. Electron. Syst., 2017)

RapidWright: Enabling Custom Crafted Implementations for FPGAs. - Chris Lavin; Alireza Kaviani (FCCM, 2018)

Build Your Own Domain-specific Solutions with RapidWright: Invited Tutorial. - Chris Lavin; Alireza Kaviani (FPGA, 2019)

An Open-Source Lightweight Timing Model for RapidWright. - Pongstorn Maidee; Chris Neely; Alireza Kaviani; Chris Lavin (FPT, 2019)

Software-like Compilation for Data Center FPGA Accelerators. - James Thomas 003; Chris Lavin; Alireza Kaviani (HEART, 2021)

RWRoute: An Open-source Timing-driven Router for Commercial FPGAs. - Yun Zhou; Pongstorn Maidee; Chris Lavin; Alireza Kaviani; Dirk Stroobandt (Zenodo, 2021)

RapidStream: Parallel Physical Implementation of FPGA HLS Designs. - Licheng Guo; Pongstorn Maidee; Yun Zhou; Chris Lavin; Jie Wang 022; Yuze Chi; Weikang Qiao; Alireza Kaviani; Zhiru Zhang; Jason Cong (FPGA, 2022)

RWRoute: An Open-source Timing-driven Router for Commercial FPGAs. - Yun Zhou; Pongstorn Maidee; Chris Lavin; Alireza Kaviani; Dirk Stroobandt (ACM Trans. Reconfigurable Technol. Syst., 2022)

Open-source and FPGAs: Hardware, Software, Both or None? - Dana How; Tim Ansell; Vaughn Betz; Chris Lavin; Ted Speers; Pierre-Emmanuel Gaillardon (FPGA, 2023)

Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling. - Chris Lavin; Eddie Hung (ICCAD, 2023)

RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. - Licheng Guo; Pongstorn Maidee; Yun Zhou; Chris Lavin; Eddie Hung; Wuxi Li; Jason Lau; Weikang Qiao; Yuze Chi; Linghao Song; Yuanlong Xiao; Alireza Kaviani; et al. (ACM Trans. Reconfigurable Technol. Syst., 2023)

DynaRapid: Fast-Tracking from C to Routed Circuits. - Andrea Guerrieri; Srijeet Guha; Chris Lavin; Eddie Hung; Lana Josipovic; Paolo Ienne (FPL, 2024)