A 65 nm CMOS tunable 0.1-to-1.6 GHz distributed transmission line N-path filter with +10 dBm blocker tolerance. - Chris M. Thomas; Lawrence E. Larson (CICC, 2014)

A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. - Chul Kim; Sohmyung Ha; Chris M. Thomas; Siddharth Joshi 001; Jongkil Park 001; Lawrence E. Larson; Gert Cauwenberghs (ESSCIRC, 2014)

A GaN HEMT N-path filter with +17 dBm jammer tolerance. - Chris M. Thomas; Lawrence E. Larson (RWS, 2015)

A pseudorandom clocking scheme for a CMOS N-path bandpass filter with 10-to-15 dB spurious leakage improvement. - Chris M. Thomas; Vincent W. Leung; Lawrence E. Larson (RWS, 2015)

A CMOS 4-channel MIMO baseband receiver with 65dB harmonic rejection over 48MHz and 50dB spatial signal separation over 3MHz at 1.3mW. - Chul Kim; Siddharth Joshi 001; Chris M. Thomas; Sohmyung Ha; Abraham Akinin; Lawrence E. Larson; Gert Cauwenberghs (VLSIC, 2015)

A 1.3 mW 48 MHz 4 Channel MIMO Baseband Receiver With 65 dB Harmonic Rejection and 48.5 dB Spatial Signal Separation. - Chul Kim; Siddharth Joshi 001; Chris M. Thomas; Sohmyung Ha; Lawrence E. Larson; Gert Cauwenberghs (IEEE J. Solid State Circuits, 2016)

A 500-MHz Bandwidth 7.5-mVpp Ripple Power-Amplifier Supply Modulator for RF Polar Transmitters. - Chul Kim; Chang-Seok Chae; Young-Sub Yuk; Chris M. Thomas; Yi-Gyeong Kim; Jong-Kee Kwon; Sohmyung Ha; Gert Cauwenberghs; Gyu-Hyeong Cho (IEEE J. Solid State Circuits, 2018)

Digitally Adaptive High-Fidelity Analog Array Signal Processing Resilient to Capacitive Multiplying DAC Inter-Stage Gain Error. - Siddharth Joshi 001; Chul Kim; Chris M. Thomas; Gert Cauwenberghs (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)