The Implementation of Fast Radix 2 Transforms on Array Processors. - Chris R. Jesshope (IEEE Trans. Computers, 1980)

Some Results Concerning Data Routing in Array Processors. - Chris R. Jesshope (IEEE Trans. Computers, 1980)

An Intelligent Pascal Editor for a Graphical Oriented Workstation. - Chris R. Jesshope; M. J. Crawley; G. L. Lovegrove (Softw. Pract. Exp., 1985)

Reconfigurable transputer systems. - Chris R. Jesshope (C³P, 1988)

Programming with active data. - Chris R. Jesshope; Philip Miller; Jelio Yantchev (Parcella, 1988)

MUNAP: an unusual computer with clear implications: Baba, TMicroprogrammable parallel computers MIT Press, Cambridge, MA, USA (1987) £26.95 pp 290. - Chris R. Jesshope (Microprocess. Microsystems, 1988)

Transputers and switches as objects in OCCAM. - Chris R. Jesshope (Parallel Comput., 1988)

High Performance Communications in Processor Networks. - Chris R. Jesshope; P. R. Miller; Jay T. Yantchev (ISCA, 1989)

Parallel processing, the transputer and the future. - Chris R. Jesshope (Microprocess. Microsystems, 1989)

Editorial. - Chris R. Jesshope (Microprocess. Microsystems, 1989)

Parallel program design: a foundation: Chandry, K M and Misra, J Addison-Wesley, Wokingham, UK (1988) £19.95 pp 516. - Chris R. Jesshope (Microprocess. Microsystems, 1989)

Distributed computer systems: Zedan, H S M (Ed.) Butterworths, Borough Green, UK (1990) £48.00, pp 313. - Chris R. Jesshope (Microprocess. Microsystems, 1990)

Simulation Facility of Distributed Memory System with "Mad Postman" Communication Network. - Vladimir Getov; Chris R. Jesshope (EDMCC, 1991)

Computing with parallel architectures: T.node: Gassilloud, D and Grossetie, J C (Eds) Kluwer (1991) pp 241, £52, ISBN 0792-31225-2. - Chris R. Jesshope (Microprocess. Microsystems, 1991)

The MP1 network chip. - Chris R. Jesshope; Cruz Izu (PDP, 1993)

The MP1 Network Chip and its Application to Parallel Computers. - Chris R. Jesshope; Cruz Izu (Comput. J., 1993)

Experimental evaluation of Mad Postman bidimensional routing networks. - Cruz Izu; Ramón Beivide; Chris R. Jesshope; Agustin Arruabarrena (Microprocess. Microprogramming, 1993)

Latency Reduction in VLSI Routers. - Chris R. Jesshope (Parallel Process. Lett., 1993)

Asynchronous packet routers. - Chris R. Jesshope; Ivailo M. Nedelchev (Interconnection Networks and Mapping and Scheduling Parallel Computations, 1994)

Basic building blocks for asynchronous packet routers. - Ivailo M. Nedelchev; Chris R. Jesshope (Great Lakes Symposium on VLSI, 1994)

Mad-postman : A Look-ahead Message Propagation Method For Static Bidimensional Meshes. - Cruz Izu; Ramón Beivide; Chris R. Jesshope (PDP, 1994)

Mechanized Reasoning and Hardware Design: C A R Hoare and M J C Gordon (Eds) Prentice Hall, Hemel Hempstead, UK (1992) ISBN 0 13 572405 8, £40, pp 151. - Chris R. Jesshope (Microprocess. Microsystems, 1994)

Parallel Boltzmann Machine Topologies for Simulated Annealing Realisation of Combinatorial Problems. - I. Ashman; T. Vladimirova; Chris R. Jesshope; R. Peel (ICANNGA, 1995)

Multiprocessing: Trade-offs in computation and communication : Vijay K Naik Kluwer Academic Publishers, Dordrecht, The Netherlands (1993) ISBN 0 7923 9370 8, Dfl 180.00, £65.50, pp224. - Chris R. Jesshope (Microprocess. Microsystems, 1995)

Optical Interconnection hardware for scalable systems. - Julian A. B. Dines; John F. Snowdon; Marc P. Y. Desmulliez; D. T. Nielson; Dima B. Barsky; Alexander V. Shafarenko; Chris R. Jesshope (PDPTA, 1996)

A FORTRAN 90 to F-code Compiler. - Horia C. Slusanschi; Chris R. Jesshope (UK Parallel, 1996)

Web based teaching: a minimalist approach. - Chris R. Jesshope (ACSE, 1997)

Optical Interconnectivity in a Scalable Data-Parallel System. - Julian A. B. Dines; John F. Snowdon; Marc P. Y. Desmulliez; Dima B. Barsky; Alexander V. Shafarenko; Chris R. Jesshope (J. Parallel Distributed Comput., 1997)

Multi-campus teaching using computer networks. - Murray Pearson; Chris R. Jesshope (ACSE, 1998)

Parallel Computer Architecture - What Is Its Future? Introduction. - Chris R. Jesshope (Euro-Par, 1999)

Computers as Tutors: Solving the Crisis in Education. - Chris R. Jesshope (J. Educ. Technol. Soc., 1999)

Micro-Threading: A New Approach to Future RISC. - Chris R. Jesshope; Bing Luo (ACAC, 2000)

Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. - Chris R. Jesshope (ACSAC, 2001)

Topic 12: Routing and Communication in Interconnection Networks. - Ramón Beivide; Chris R. Jesshope; Antonio Robles; Cruz Izu (Euro-Par, 2001)

Technology Integrated Learning Environment - A Web-based Distance Learning System. - Regina Gehne; Chris R. Jesshope; Zhenzi Zhang (IMSA, 2001)

Adaptivity in Web-based Educational System. - Hong Hong; Neena Albi; Kinshuk; Xiaoqin He; Ashok Patel; Chris R. Jesshope (WWW Posters, 2001)

Cost-Effective Multimedia in On-line Teaching. - Chris R. Jesshope (J. Educ. Technol. Soc., 2001)

Multi-threaded Microprocessors - Evolution or Revolution. - Chris R. Jesshope (Asia-Pacific Computer Systems Architecture Conference, 2003)

Web Services Technology and Learning Technology- A Web-Services Model for Constructing Decentralized Virtual Learning Environments. - Lipeng Wen; Chris R. Jesshope (ICWS, 2003)

Microgrids - The exploitation of massive on-chip concurrency. - Chris R. Jesshope (High Performance Computing Workshop, 2004)

A General Learning Management System Based on Schema-driven Methodology. - Lipeng Wen; Chris R. Jesshope (ICALT, 2004)

Scalable Instruction-Level Parallelism.. - Chris R. Jesshope (SAMOS, 2004)

The Challenges of Massive On-Chip Concurrency. - Kostas Bousias; Chris R. Jesshope (Asia-Pacific Computer Systems Architecture Conference, 2005)

muTC - An Intermediate Language for Programming Chip Multiprocessors. - Chris R. Jesshope (Asia-Pacific Computer Systems Architecture Conference, 2006)

Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors. - Nabil Hasasneh; Ian M. Bell; Chris R. Jesshope (ARCS, 2006)

A Model for the Design and Programming of Multi-cores. - Chris R. Jesshope (High Performance Computing Workshop, 2006)

Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors. - Kostas Bousias; Nabil Hasasneh; Chris R. Jesshope (Comput. J., 2006)

Supporting Microthread Scheduling and Synchronisation in CMPs. - Ian M. Bell; Nabil Hasasneh; Chris R. Jesshope (Int. J. Parallel Program., 2006)

Special issue on Micro-grids - Guest Editor Introduction. - Chris R. Jesshope; Alexander V. Shafarenko (Int. J. Parallel Program., 2006)

Guest Editor's Introduction (Part 2). - Chris R. Jesshope; Alexander V. Shafarenko (Int. J. Parallel Program., 2006)

Microthreading a Model for Distributed Instruction-level Concurrency. - Chris R. Jesshope (Parallel Process. Lett., 2006)

High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids. - Nabil Hasasneh; Ian M. Bell; Chris R. Jesshope (AICCSA, 2007)

On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores. - Li Zhang 034; Chris R. Jesshope (Euro-Par Workshops, 2007)

Formalizing SANE Virtual Processor in Thread Algebra. - Thuy Duong Vu; Chris R. Jesshope (ICFEM, 2007)

Strategies for Compiling µ TC to Novel Chip Multiprocessors. - Thomas A. M. Bernard; Chris R. Jesshope; Peter M. W. Knijnenburg (SAMOS, 2007)

Asynchronous arbiter for micro-threaded chip multiprocessors. - Nabil Hasasneh; Ian M. Bell; Chris R. Jesshope (J. Syst. Archit., 2007)

Concurrency engineering. - Chris R. Jesshope; Alexander V. Shafarenko (ACSAC, 2008)

The Verification of the On-Chip COMA Cache Coherence Protocol. - Thuy Duong Vu; Li Zhang 034; Chris R. Jesshope (AMAST, 2008)

Building a Concurrency and Resource Allocation Model into a Processor's ISA. - Chris R. Jesshope (Euro-Par Workshops, 2008)

A general model of concurrency and its implementation as many-core dynamic RISC processors. - Thomas A. M. Bernard; Kostas Bousias; Liang Guang; Chris R. Jesshope; Mike Lankamp; Michiel W. van Tol; Li Zhang 034 (ICSAMOS, 2008)

Introduction to Programming Multicores. - Chris R. Jesshope (SAMOS, 2008)

An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency. - Chris R. Jesshope; Jean-Marc Philippe; Michiel W. van Tol (SAMOS, 2008)

Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips. - Chris R. Jesshope (Parallel Process. Lett., 2008)

Evaluating CMPs and Their Memory Architecture. - Chris R. Jesshope; Mike Lankamp; Li Zhang 034 (ARCS, 2009)

HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? - Martti Forsell; H. Peter Hofstee; Ahmed Jerraya; Chris R. Jesshope; Uzi Vishkin; Jesper Larsson Träff (Euro-Par Workshops, 2009)

Making multi-cores mainstream - from security to scalability. - Chris R. Jesshope; Michael A. Hicks 001; Mike Lankamp; Raphael 'kena' Poss; Li Zhang 034 (PARCO, 2009)

Implementation and evaluation of a microthread architecture. - Kostas Bousias; Liang Guang; Chris R. Jesshope; Mike Lankamp (J. Syst. Archit., 2009)

An implementation of the SANE Virtual Processor using POSIX threads. - Michiel W. van Tol; Chris R. Jesshope; Mike Lankamp; Simon Polstra (J. Syst. Archit., 2009)

The implementation of an SVP many-core processor and the evaluation of its memory architecture. - Chris R. Jesshope; Mike Lankamp; Li Zhang 034 (SIGARCH Comput. Archit. News, 2009)

Resource-Agnostic Programming for Many-Core Microgrids. - Thomas A. M. Bernard; Clemens Grelck; Michael A. Hicks 001; Chris R. Jesshope; Raphael Poss (Euro-Par Workshops, 2010)

An Operating System Strategy for General-purpose Parallel Computing on Many-core Architectures. - Michiel W. van Tol; Chris R. Jesshope (High Performance Computing Workshop, 2010)

Towards scalable I/O on a many-core architecture. - Michael A. Hicks 001; Michiel W. van Tol; Chris R. Jesshope (ICSAMOS, 2010)

On the Compilation of a Language for General Concurrent Target Architectures. - Thomas A. M. Bernard; Clemens Grelck; Chris R. Jesshope (Parallel Process. Lett., 2010)

A Micro Threading Based Concurrency Model for Parallel Computing. - Qiang Yang 006; Chris R. Jesshope; Jian Fu (IPDPS Workshops, 2011)

Efficient Memory Copy Operations on the 48-core Intel SCC Processor. - Michiel W. van Tol; Roy Bakker; Merijn Verstraaten; Clemens Grelck; Chris R. Jesshope (MARC Symposium, 2011)

Mapping Distributed S-Net on the 48-core Intel SCC processor. - Merijn Verstraaten; Clemens Grelck; Michiel W. van Tol; Roy Bakker; Chris R. Jesshope (MARC Symposium, 2011)

Engineering Concurrent Software Guided by Statistical Performance Analysis. - Clemens Grelck; Kevin Hammond; Heinz Hertlein; Philip K. F. Hölzenspies; Chris R. Jesshope; Raimund Kirner; Bernd Scheuermann; Alexander V. Shafarenko; Iraneus te Boekhorst; Volkmar Wieser (PARCO, 2011)

High Level Simulation of SVP Many-Core Systems. - Muhammad Irfan Uddin; Michiel W. van Tol; Chris R. Jesshope (Parallel Process. Lett., 2011)

Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. - Raphael Poss; Mike Lankamp; Qiang Yang 006; Jian Fu; Michiel W. van Tol; Chris R. Jesshope (DSD, 2012)

Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores. - Muhammad Irfan Uddin; Chris R. Jesshope; Michiel W. van Tol; Raphael Poss (RAPIDO, 2012)

On-demand thread-level fault detection in a concurrent programming environment. - Jian Fu; Qiang Yang 006; Raphael Poss; Chris R. Jesshope; Chunyuan Zhang (ICSAMOS, 2013)

MGSim - A simulation environment for multi-core research and education. - Raphael Poss; Mike Lankamp; Qiang Yang 006; Jian Fu; Muhammad Irfan Uddin; Chris R. Jesshope (ICSAMOS, 2013)

MGSim - Simulation tools for multi-core processor architectures - Mike Lankamp; Raphael 'kena' Poss; Qiang Yang 006; Jian Fu; Muhammad Irfan Uddin; Chris R. Jesshope (CoRR, 2013)

Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management. - Raphael Poss; Mike Lankamp; Qiang Yang 006; Jian Fu; Michiel W. van Tol; Muhammad Irfan Uddin; Chris R. Jesshope (Microprocess. Microsystems, 2013)

Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors. - Jian Fu; Qiang Yang 006; Raphael Poss; Chris R. Jesshope; Chunyuan Zhang (ARES, 2014)

A fault detection mechanism in a Data-flow scheduled Multithreaded processor. - Jian Fu; Qiang Yang 006; Raphael Poss; Chris R. Jesshope; Chunyuan Zhang (DATE, 2014)

Analytical-Based High-Level Simulation of the Microthreaded Many-Core Architectures. - Muhammad Irfan Uddin; Raphael Poss; Chris R. Jesshope (PDP, 2014)

Signature-based high-level simulation of microthreaded many-core architectures. - Muhammad Irfan Uddin; Raphael Poss; Chris R. Jesshope (SIMULTECH, 2014)

Cache-based high-level simulation of microthreaded many-core architectures. - Muhammad Irfan Uddin; Raphael Poss; Chris R. Jesshope (J. Syst. Archit., 2014)

On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches. - Qiang Yang 006; Jian Fu; Raphael Poss; Chris R. Jesshope (ACM Trans. Embed. Comput. Syst., 2014)