VLSI physics. - Christer Svensson (Integr., 1983)

NORCHIP, a silicon brokers model. - Ole Olesen; Christer Svensson (Integr., 1984)

Signal resynchronization in VLSI systems. - Christer Svensson (Integr., 1986)

Guest editorial. - Christer Svensson (Integr., 1987)

Fully Dynamic Switch-Level Simulation of CMOS Circuits. - Rolf Sundblad; Christer Svensson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Switch-level simulation and the pass transistor EXOR gate. - Christer Svensson; Robert Tjärnström (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

High-speed CMOS circuit technique. - Jiren Yuan; Christer Svensson (IEEE J. Solid State Circuits, 1989)

Single-Chip High-Speed Computation of Optical Flow. - Per-Erik Danielsson; Pär Emanuelsson; Keping Chen; Per Ingelhag; Christer Svensson (MVA, 1990)

A unified single-phase clocking scheme for VLSI systems. - Morteza Afghahi; Christer Svensson (IEEE J. Solid State Circuits, 1990)

Performance of Synchronous and Asynchronous Schemes for VLSI Systems. - Morteza Afghahi; Christer Svensson (IEEE Trans. Computers, 1992)

System Level Policies for Fault Tolerance Issues in the FERMI Project. - A. Dell'Acqua; M. Hansen; Sami J. Inkinen; B. Lofstedt; J. P. Vanuxem; Christer Svensson; Jiren Yuan; H. Hentzell; L. Del Buono; J. David; J. F. Genat; H. Lebbolo; et al. (DFT, 1993)

A sensor array for phase and amplitude detection of synchronous modulated light sources. - Christer Jansson; Christer Svensson (ISCAS, 1993)

Ultra high speed CMOS design. - Christer Svensson; Jiren Yuan (VLSI, 1993)

Single-chip image sensors with a digital processor array. - Robert Forchheimer; Keping Chen; Christer Svensson; Anders Ödmark (J. VLSI Signal Process., 1993)

Trading speed for low power by choice of supply and threshold voltages. - Dake Liu; Christer Svensson (IEEE J. Solid State Circuits, 1993)

A 700-MHz 24-b pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillator. - Fang Lu; Henry Samueli; Jiren Yuan; Christer Svensson (IEEE J. Solid State Circuits, 1993)

5.8Gb/s 16: 1 Multiplexer and 1: 16 Demultiplexer Using 1.2µm BiCMOS. - Jacob Midtgaard; Christer Svensson (ISCAS, 1994)

Noise in digital dynamic CMOS circuits. - Patrik Larsson; Christer Svensson (IEEE J. Solid State Circuits, 1994)

Impact of clock slope on true single phase clocked (TSPC) CMOS circuits. - Patrik Larsson; Christer Svensson (IEEE J. Solid State Circuits, 1994)

Power consumption estimation in CMOS VLSI chips. - Dake Liu; Christer Svensson (IEEE J. Solid State Circuits, 1994)

VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept. - Jan-Erik Eklund; Christer Svensson; Anders Åström (IEEE Trans. Very Large Scale Integr. Syst., 1996)

New single-clock CMOS latches and flipflops with improved speed and power savings. - Jiren Yuan; Christer Svensson (IEEE J. Solid State Circuits, 1997)

Efficient High-Speed CMOS Design by Layout Based Schematic Method. - Fenghao Mu; Christer Svensson (EUROMICRO, 1998)

Self-Synchronized Vector Transfer for High Speed Parallel Systems. - Fenghao Mu; Christer Svensson (ICPADS, 1998)

Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. - Atila Alvandpour; Per Larsson-Edefors; Christer Svensson (ISLPED, 1998)

Low power and low voltage CMOS digital circuit techniques. - Christer Svensson; Atila Alvandpour (ISLPED, 1998)

Time resolution of NMOS sampling switches used on low-swing signals. - Henrik O. Johansson; Christer Svensson (IEEE J. Solid State Circuits, 1998)

A leakage-tolerant multi-phase keeper for wide domino circuits. - Atila Alvandpour; Per Larsson-Edefors; Christer Svensson (ICECS, 1999)

A novel mixed analog/digital MAC unit implemented with SC technique suitable for fully programmable narrow-band FIR filter applications. - Mattias Duppils; Jan-Erik Eklund; Christer Svensson (ICECS, 1999)

High speed interface for system-on-chip design by self-tested self-synchronization. - Fenghao Mu; Christer Svensson (ISCAS (2), 1999)

High speed multistage CMOS clock buffers with pulse width control loop. - Fenghao Mu; Christer Svensson (ISCAS (2), 1999)

Methodology of layout based schematic and its usage in efficient high performance CMOS design. - Fenghao Mu; Christer Svensson (ISCAS (6), 1999)

Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems. - Fenghao Mu; Christer Svensson (IEEE Trans. Parallel Distributed Syst., 1999)

A layout-based schematic method for very high-speed CMOS cell design. - Fenghao Mu; Christer Svensson (IEEE Trans. Very Large Scale Integr. Syst., 1999)

GLMC: interconnect length estimation by growth-limited multifold clustering. - Atila Alvandpour; Per Larsson-Edefors; Christer Svensson (ISCAS, 2000)

Low power mixed analog-digital signal processing. - Mattias Duppils; Christer Svensson (ISLPED, 2000)

Optimized test circuits for SER characterization of a manufacturing process. - Peter Hazucha; Christer Svensson (IEEE J. Solid State Circuits, 2000)

Cosmic-ray soft error rate characterization of a standard 0.6-μm CMOS process. - Peter Hazucha; Christer Svensson; Stephen A. Wender (IEEE J. Solid State Circuits, 2000)

Pulsewidth control loop in high-speed CMOS clock buffers. - Fenghao Mu; Christer Svensson (IEEE J. Solid State Circuits, 2000)

3V CMOS 0.35 µ transimpedance receiver for optical applications. - Håkan Bengtson; Christer Svensson (ISCAS (4), 2001)

Modeling of dynamic errors in algorithmic A/D converters. - Kalle Folkesson; Christer Svensson; Jan-Erik Eklund (ISCAS (5), 2001)

A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6-μm CMOS. - Anders Edman; Jacob Christensen 002; Anders Emrich; Christer Svensson (IEEE J. Solid State Circuits, 2001)

Optimum voltage swing on on-chip and off-chip interconnect. - Christer Svensson (IEEE J. Solid State Circuits, 2001)

Application of Knowledge-based System in a B-to-B Environment. - Martin Malis; Christer Svensson; Lars Hvam (IMSA, 2002)

A 1 GHz linearized CMOS track-and-hold circuit. - Darius Jakonis; Christer Svensson (ISCAS (5), 2002)

Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). - Stefan Rusu; Manoj Sachdev; Christer Svensson; Bram Nauta (ASP-DAC/VLSI Design, 2002)

Electrical interconnects revitalized. - Christer Svensson (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Full-custom vs. standard-cell design flow: an adder case study. - Henrik Eriksson; Per Larsson-Edefors; Tomas Henriksson; Christer Svensson (ASP-DAC, 2003)

Bitline leakage equalization for sub-100nm caches. - Atila Alvandpour; Dinesh Somasekhar; Ram Krishnamurthy 001; Vivek De; Shekhar Borkar; Christer Svensson (ESSCIRC, 2003)

A 1.6 GHz downconversion sampling mixer in CMOS. - Darius Jakonis; Christer Svensson (ISCAS (1), 2003)

Synchronous Latency Insensitive Design. - Christer Svensson (ASYNC, 2004)

Timing closure through a globally synchronous, timing partitioned design methodology. - Anders Edman; Christer Svensson (DAC, 2004)

A low-swing single-ended L1 cache bus technique for sub-90nm technologies. - Peter Caputa; Mark A. Anders 001; Christer Svensson; Ram K. Krishnamurthy; Shekhar Borkar (ESSCIRC, 2004)

2 GB/S decision feedback equalizer in 3.3 V 0.35 µM CMOS. - Håkan Bengtson; Christer Svensson (Circuits, Signals, and Systems, 2004)

A new mesochronous clocking scheme for synchronization in SoC. - Behzad Mesgarzadeh; Christer Svensson; Atila Alvandpour (ISCAS (2), 2004)

An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies. - Peter Caputa; Henrik Fredriksson; Martin Hansson; Stefan Back Andersson; Atila Alvandpour; Christer Svensson (PATMOS, 2004)

A scalable and robust rail-to-rail delay cell for DLLs. - Håkan Bengtson; Christer Svensson (SoCC, 2004)

Robust multi-phase clock generation with reduced jitter. - Kalle Folkesson; Christer Svensson (SoCC, 2004)

Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study. - Henrik Fredriksson; Christer Svensson (SoCC, 2004)

A high-level dynamic-error model of a pipelined analog-to-digital converter. - Kalle Folkesson; Christer Svensson; B. Knuthammar; A. Dreyfert (ISCAS (6), 2005)

Synchronous latency-insensitive design for multiple clock domain. - Anders Edman; Christer Svensson; Behzad Mesgarzadeh (SoCC, 2005)

A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS. - Darius Jakonis; Kalle Folkesson; Jerzy J. Dabrowski; Patrik Eriksson; Christer Svensson (IEEE J. Solid State Circuits, 2005)

Well-behaved global on-chip interconnect. - Peter Caputa; Christer Svensson (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

SC filter for RF down conversion with wideband image rejection. - Stefan Back Andersson; Jerzy J. Dabrowski; Christer Svensson; J. Konopacki (ISCAS, 2006)

An on-chip delay- and skew-insensitive multicycle communication scheme. - Peter Caputa; Christer Svensson (ISSCC, 2006)

A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency. - Peter Caputa; Christer Svensson (VLSI Design, 2006)

Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS. - Stefan Back Andersson; Rashad Ramzan; Jerzy J. Dabrowski; Christer Svensson (ECCTD, 2007)

A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS. - Rashad Ramzan; Stefan Back Andersson; Jerzy J. Dabrowski; Christer Svensson (ISSCC, 2007)

3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus. - Henrik Fredriksson; Christer Svensson (SoC, 2007)

Analog Power Modelling. - Christer Svensson (PATMOS, 2007)

2.6 Gb/s over a four-drop bus using an adaptive 12-tap DFE. - Henrik Fredriksson; Christer Svensson (ESSCIRC, 2008)

Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters. - Timmy Sundström; Boris Murmann; Christer Svensson (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS. - Jonas Fritzin; Christer Svensson; Atila Alvandpour (ESSCIRC, 2010)

A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS. - Timmy Sundström; Christer Svensson; Atila Alvandpour (ESSCIRC, 2010)

Envelope detector sensitivity and blocking characteristics. - Emil Nilsson; Christer Svensson (ECCTD, 2011)

Power consumption bounds for SAR ADCs. - Dai Zhang; Christer Svensson; Atila Alvandpour (ECCTD, 2011)

A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE. - Jonas Fritzin; Christer Svensson; Atila Alvandpour (ESSCIRC, 2011)

A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS. - Timmy Sundström; Christer Svensson; Atila Alvandpour (IEEE J. Solid State Circuits, 2011)

Design and Analysis of a Class-D Stage With Harmonic Suppression. - Jonas Fritzin; Christer Svensson; Atila Alvandpour (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS. - Jonas Fritzin; Christer Svensson; Atila Alvandpour (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Resource efficient implementation of a 10Gb/s radio receiver baseband in FPGA. - Christer Svensson; Zhongxia Simon He; Herbert Zirath; Lei Bao; Jingjing Chen (FPGAworld, 2013)

Ultra Low Power Wake-Up Radio Using Envelope Detector and Transmission Line Voltage Transformer. - Emil Nilsson; Christer Svensson (IEEE J. Emerg. Sel. Topics Circuits Syst., 2013)

A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain. - Nasim Farahini; Ahmed Hemani; Anders Lansner; Fabien Clermidy; Christer Svensson (ASP-DAC, 2014)

Power Consumption of Integrated Low-Power Receivers. - Emil Nilsson; Christer Svensson (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS. - Timmy Sundström; Javad Bagheri Asli; Christer Svensson; Atila Alvandpour (NorCAS, 2020)