A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. - Didier Lattard; Edith Beigné; Christian Bernard; Catherine Bour; Fabien Clermidy; Yves Durand; Jean Durupt; Didier Varreau; Pascal Vivet; Pierre Penard; Arnaud Bouttier; Friedbert Berens (ISSCC, 2007)

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. - Bettina Rebaud; Marc Belleville; Christian Bernard; Zeqin Wu; Michel Robert; Philippe Maurine; Nadine Azémard (ISVLSI, 2008)

A Microprogrammable Memory Controller for high-performance dataflow applications. - Jérôme Martin; Christian Bernard; Fabien Clermidy; Yves Durand (ESSCIRC, 2009)

Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. - Bettina Rebaud; Marc Belleville; Edith Beigné; Christian Bernard; Michel Robert; Philippe Maurine; Nadine Azémard (PATMOS, 2009)

A 477mW NoC-based digital baseband for MIMO 4G SDR. - Fabien Clermidy; Christian Bernard; Romain Lemaire; Jérôme Martin; Ivan Miro Panades; Yvain Thonnart; Pascal Vivet; Norbert Wehn (ISSCC, 2010)

A low-power VLIW processor for 3GPP-LTE complex numbers processing. - Christian Bernard; Fabien Clermidy (DATE, 2011)

Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. - Bettina Rebaud; Marc Belleville; Edith Beigné; Christian Bernard; Michel Robert; Philippe Maurine; Nadine Azémard (Microelectron. J., 2011)

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. - Robin Wilson; Edith Beigné; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; et al. (ISSCC, 2014)

3D advanced integration technology for heterogeneous systems. - Pascal Vivet; Christian Bernard; Fabien Clermidy; Denis Dutoit; Eric Guthmuller; Ivan Miro Panades; Gaël Pillonnet; Yvain Thonnart; Arnaud Garnier; Didier Lattard; Amandine Jouve; Franck Bana; et al. (3DIC, 2015)

Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. - Pascal Vivet; Christian Bernard; Eric Guthmuller; Ivan Miro Panades; Yvain Thonnart; Fabien Clermidy (ISVLSI, 2015)

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. - Edith Beigné; Alexandre Valentian; Ivan Miro Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; et al. (IEEE J. Solid State Circuits, 2015)

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Cristiano Santos; Fabien Clermidy; Séverine Cheramy; Frédéric Pétrot; et al. (ISSCC, 2016)

Distributed Dynamic Rate Adaptation on a Network on Chip with Traffic Distortion. - Yves Durand; Christian Bernard; Fabien Clermidy (MCSoC, 2016)

A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems. - Yves Durand; Christian Bernard; Romain Lemaire; César Fuguet Tortolero; Emilie Garat (DSD, 2017)

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Cristiano Santos; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Denis Dutoit; Fabien Clermidy; Séverine Cheramy; et al. (IEEE J. Solid State Circuits, 2017)

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. - Eric Guthmuller; César Fuguet Tortolero; Pascal Vivet; Christian Bernard; Ivan Miro Panades; Jean Durupt; E. Beignc; Didier Lattard; Séverine Cheramy; Alain Greiner; Quentin L. Meunier; Pirouz Bazargan-Sabet (ESSCIRC, 2018)

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems. - Yvain Thonnart; Stéphane Bernabé; Jean Charbonnier; Christian Bernard; David Coriat; César Fuguet Tortolero; Pierre Tissier; Benoît Charbonnier; Stéphane Malhouitre; Damien Saint-Patrice; Myriam Assous; Aditya Narayan; et al. (DATE, 2020)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)

Navigating SMEs' Innovation in the Digital Age: From Manufacturing to Servitization. - Claudia Pelletier; Mbarek El Bounjimi; Christian Bernard; Marc-André Gaudreau (AMCIS, 2023)