A 1.2V 56mW 10 bit 165Ms/s pipeline-ADC for HD-video applications. - Martin Trojer; Mauro Cleris; Ulrich Gaier; Thomas Hebein; Peter Pridnig; Bernhard Kuttin; Bernhard Tschuden; Christian Krassnitzer; Christian Kuttin; Wolfgang Pribyl (ESSCIRC, 2008)

A 1.2 V 4.5 mW 10 bit 8 MS/s cyclic-ADC for mobile video and sensor applications. - Martin Trojer; Thomas Hebein; Christian Krassnitzer; Alfons Hammerl; Mauro Cleris; Ulrich Gaier; Bernhard Kuttin; Peter Pridnig; Thomas Niederfriniger; Bernhard Tschuden (Elektrotech. Informationstechnik, 2009)

A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS. - Edwin Thaller; Run Levinger; Evgeny Shumaker; Aryeh Farber; Sergey Bershansky; Nir Geron; Ashoke Ravi; Rotem Banin; Jasmin Kadry; Gil Horovitz; Christian Krassnitzer; Christoph Duller; et al. (ISSCC, 2021)