SURF - A Program for Modeling and Reliability Prediction for Fault-Tolerant Computing Systems. - Christian Landrault; Jean-Claude Laprie (Jerusalem Conference on Information Technology, 1978)

Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults. - Alain Costes; Christian Landrault; Jean-Claude Laprie (IEEE Trans. Computers, 1978)

Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor. - Yves Crouzet; Christian Landrault (IEEE Trans. Computers, 1980)

Fault modelling and fault equivalence in CMOS technology. - Marie-Lise Flottes; Christian Landrault; Serge Pravossoudovitch (EURO-DAC, 1990)

Fault modeling and fault equivalence in CMOS technology. - Marie-Lise Flottes; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 1991)

A Novel Approach to Delay-Fault Diagnosis. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (DAC, 1992)

A New Reliable Method for Delay-Fault Diagnosis. - Marie-Lise Flottes; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (VLSI Design, 1992)

Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors. - Lew Fock Chong Lew Yan Voon; Christian Dufaza; Christian Landrault (VLSI Design, 1992)

BIST linear generator based on complemented outputs. - Lew Fock Chong Lew Yan Voon; Christian Dufaza; Christian Landrault (VTS, 1992)

Delay-Fault Diagnosis by Critical-Path Tracing. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (IEEE Des. Test Comput., 1992)

An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. - D. Dumas; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (ITC, 1993)

Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. - D. Dumas; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (EDAC-ETC-EUROASIC, 1994)

Test configurations to enhance the testability of sequential circuits. - S. Lavabre; Yves Bertrand; Michel Renovell; Christian Landrault (Asian Test Symposium, 1995)

A trace-based method for delay fault diagnosis in synchronous sequential circuits. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (ED&TC, 1995)

Is High-Level Test Synthesis Just Design for Test? - Christian Landrault; Marie-Lise Flottes; Bruno Rouzeyre (ITC, 1995)

Diagnostic of path and gate delay faults in non-scan sequential circuits. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (VTS, 1995)

An advanced diagnostic method for delay faults in combinational faulty circuits. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 1995)

Delay fault diagnosis in sequential circuits based on path tracing. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (Integr., 1995)

DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. - P. Cavallera; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (ED&TC, 1996)

A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (ITC, 1996)

A new test pattern generation method for delay fault testing. - S. Cremoux; Christophe Fagot; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (VTS, 1996)

Automatic Testability Analysis of Boards and MCMs at Chip Level. - Marc Perbost; Ludovic Le Lan; Christian Landrault (Asian Test Symposium, 1997)

A gate resizing technique for high reduction in power consumption. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; D. Severac (ISLPED, 1997)

On Using Machine Learning for Logic BIST. - Christophe Fagot; Patrick Girard 001; Christian Landrault (ITC, 1997)

Hardware Test: Can We Learn from Software Testing? - J. Abraham; Phyllis G. Frankl; Christian Landrault; Meryem Marzouki; Paolo Prinetto; Chantal Robach; Pascale Thévenod-Fosse (VTS, 1997)

An optimized BIST test pattern generator for delay testing. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch (VTS, 1997)

A non-iterative gate resizing algorithm for high reduction in power consumption. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; D. Severac (Integr., 1997)

A BIST Structure to Test Delay Faults in a Scan Environment. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch; Arnaud Virazel (Asian Test Symposium, 1998)

Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 1999)

Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts. - A. Toulouse; David Bernard; Christian Landrault; Pascal Nouet (DATE, 1999)

On calculating efficient LFSR seeds for built-in self test. - Christophe Fagot; Olivier Gascuel; Patrick Girard 001; Christian Landrault (ETW, 1999)

Partial set for flip-flops based on state requirement for non-scan BIST scheme. - Marie-Lise Flottes; Christian Landrault; A. Petitqueux (ETW, 1999)

A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Great Lakes Symposium on VLSI, 1999)

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Joan Figueras; Salvador Manich; João Paulo Teixeira 001; Marcelino B. Santos (ISCAS (1), 1999)

A Test Vector Inhibiting Technique for Low Energy BIST Design. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (VTS, 1999)

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 1999)

Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. - Marie-Lise Flottes; Christian Landrault; A. Petitqueux (Asian Test Symposium, 2000)

An adjacency-based test pattern generator for low power BIST design. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 2000)

Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (IOLTW, 2000)

Low power BIST design by hypergraph partitioning: methodology and architectures. - Patrick Girard 001; Christian Landrault; Loïs Guiller; Serge Pravossoudovitch (ITC, 2000)

Hidden Markov and Independence Models with Patterns for Sequential BIST. - Laurent Bréhélin; Olivier Gascuel; Gilles Caraux; Patrick Girard 001; Christian Landrault (VTS, 2000)

Low Power BIST by Filtering Non-Detecting Vectors. - Salvador Manich; A. Gabarró; M. Lopez; Joan Figueras; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; João Paulo Teixeira 001; Marcelino B. Santos (J. Electron. Test., 2000)

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 2001)

Interconnect Capacitance Modelling in a VDSM CMOS Technology. - David Bernard; Christian Landrault; Pascal Nouet (VLSI-SOC, 2001)

Random Adjacent Sequences: An Efficient Solution for Logic BIST. - René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VLSI-SOC, 2001)

A Gated Clock Scheme for Low Power Scan-Based BIST. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (IOLTW, 2001)

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Hans-Joachim Wunderlich (VTS, 2001)

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. - Arnaud Virazel; René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 2001)

Test Power: a Big Issue in Large SOC Designs. - Yannick Bonhomme; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (DELTA, 2002)

Power Driven Chaining of Flip-Flops in Scan Architectures. - Yannick Bonhomme; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (ITC, 2002)

On Using Efficient Test Sequences for BIST. - René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2002)

High Defect Coverage with Low-Power Test Sequences in a BIST Environment. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Hans-Joachim Wunderlich (IEEE Des. Test Comput., 2002)

Hardware Generation of Random Single Input Change Test Sequences. - René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2002)

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (ITC, 2003)

A Ring Architecture Strategy for BIST Test Pattern Generation. - Christophe Fagot; Olivier Gascuel; Patrick Girard 001; Christian Landrault (J. Electron. Test., 2003)

A Unified DFT Approach for BIST and External Test. - Marie-Lise Flottes; Christian Landrault; A. Petitqueux (J. Electron. Test., 2003)

Guest Editorial. - Christian Landrault (J. Electron. Test., 2003)

Design of Routing-Constrained Low Power Scan Chains. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DELTA, 2004)

Power-Driven Routing-Constrained Scan Chain Design. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 2004)

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. - Nabil Badereddine; Patrick Girard 001; Arnaud Virazel; Serge Pravossoudovitch; Christian Landrault (PATMOS, 2005)

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. - Nabil Badereddine; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Christian Landrault (VLSI-SoC, 2005)

Power-Aware Test Data Compression for Embedded IP Cores. - Nabil Badereddine; Zhanglei Wang; Patrick Girard 001; Krishnendu Chakrabarty; Serge Pravossoudovitch; Christian Landrault (ATS, 2006)

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. - Nabil Badereddine; Patrick Girard 001; Serge Pravossoudovitch; Christian Landrault; Arnaud Virazel; Hans-Joachim Wunderlich (VLSI-SoC, 2006)

An Overview of Failure Mechanisms in Embedded Flash Memories. - Olivier Ginez; Jean Michel Daga; Marylene Combe; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2006)

A Gated Clock Scheme for Low Power Testing of Logic Cores. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2006)

Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. - Magali Bastian; Vincent Gouin; Patrick Girard 001; Christian Landrault; Alexandre Ney; Serge Pravossoudovitch; Arnaud Virazel (ATS, 2007)

Fast Bridging Fault Diagnosis using Logic Information. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ATS, 2007)

Slow write driver faults in 65nm SRAM technology: analysis and March test solution. - Alexandre Ney; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (DATE, 2007)

A Mixed Approach for Unified Logic Diagnosis. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DDECS, 2007)

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ETS, 2007)

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. - Alexandre Ney; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (ETS, 2007)

DERRIC: A Tool for Unified Logic Diagnosis. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ETS, 2007)

A concurrent approach for testing address decoder faults in eFlash memories. - Olivier Ginez; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Jean Michel Daga (ITC, 2007)

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2007)

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. - Alexandre Ney; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (VTS, 2007)

Editorial. - Christian Landrault; Erik Jan Marinissen (IET Comput. Digit. Tech., 2007)

Improving Diagnosis Resolution without Physical Information. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DELTA, 2008)

Using TMR Architectures for Yield Improvement. - Julien Vial; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DFT, 2008)

Yield Improvement, Fault-Tolerance to the Rescue?. - Julien Vial; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (IOLTS, 2008)

SoC Yield Improvement: Redundant Architectures to the Rescue? - Julien Vial; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ITC, 2008)

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. - Nabil Badereddine; Zhanglei Wang; Patrick Girard 001; Krishnendu Chakrabarty; Arnaud Virazel; Serge Pravossoudovitch; Christian Landrault (J. Electron. Test., 2008)

Something I Always Wanted to Know About Test, But Was Afraid to Ask. - Christian Landrault (ETS, 2009)

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2009)

Is triple modular redundancy suitable for yield improvement? - Julien Vial; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (IET Comput. Digit. Tech., 2009)