Low Power CORDIC Implementation Using Redundant Number Representation. - Christian V. Schimpfle; Sven Simon 001; Josef A. Nossek (ASAP, 1997)

High-level circuit modeling for power estimation. - Christian V. Schimpfle; Sven Simon 001; Josef A. Nossek (ICECS, 1999)

Device level based cell modeling for fast power estimation. - Christian V. Schimpfle; Sven Simon 001; Josef A. Nossek (ISCAS (1), 1999)

Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms. - Peter Rieder; Sven Simon 001; Christian V. Schimpfle (J. VLSI Signal Process., 1999)

Automated transistor sizing algorithm for minimizing spurious switching activities in CMOS circuits. - Artur Wróblewski; Christian V. Schimpfle; Josef A. Nossek (ISCAS, 2000)

Minimizing gate capacitances with transistor sizing. - Artur Wróblewski; Otto Schumacher; Christian V. Schimpfle; Josef A. Nossek (ISCAS (4), 2001)

Minimizing Spurious Switching Activities with Transistor Sizing. - Artur Wróblewski; Christian V. Schimpfle; Otto Schumacher; Josef A. Nossek (VLSI Design, 2002)