Design space exploration for 3D-stacked DRAMs. - Christian Weis; Norbert Wehn; Igor Loi; Luca Benini (DATE, 2011)

Bringing C++ productivity to VHDL world: From language definition to a case study. - Ivan Shcherbakov; Christian Weis; Norbert Wehn (FDL, 2011)

DRAM selection and configuration for real-time mobile systems. - Manil Dev Gomony; Christian Weis; Benny Akesson; Norbert Wehn; Kees Goossens (DATE, 2012)

An energy efficient DRAM subsystem for 3D integrated SoCs. - Christian Weis; Igor Loi; Luca Benini; Norbert Wehn (DATE, 2012)

ASIC design of a Gbit/s LDPC decoder for iterative MIMO systems. - Christina Gimmler; Frank Kienle; Christian Weis; Norbert Wehn; Matthias Alles (ICNC, 2012)

A High-Performance FPGA-Based Implementation of the LZSS Compression Algorithm. - Ivan Shcherbakov; Christian Weis; Norbert Wehn (IPDPS Workshops, 2012)

A 2.15GBit/s turbo code decoder for LTE advanced base station applications. - Thomas Ilnseher; Frank Kienle; Christian Weis; Norbert Wehn (ISTC, 2012)

Design Space of Flexible Multigigabit LDPC Decoders. - Philipp Schläfer; Christian Weis; Norbert Wehn; Matthias Alles (VLSI Design, 2012)

Towards variation-aware system-level power estimation of DRAMs: an empirical approach. - Karthik Chandrasekar 001; Christian Weis; Benny Akesson; Norbert Wehn; Kees Goossens (DAC, 2013)

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs. - Karthik Chandrasekar 001; Christian Weis; Benny Akesson; Norbert Wehn; Kees Goossens (DATE, 2013)

Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ. - MohammadSadegh Sadri; Christian Weis; Norbert Wehn; Luca Benini (FPGAworld, 2013)

TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration. - Matthias Jung 001; Christian Weis; Norbert Wehn; Karthik Chandrasekar 001 (RAPIDO, 2013)

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience. - Veit Kleeberger; Christina Gimmler-Dumont; Christian Weis; Andreas Herkersdorf; Daniel Mueller-Gritschneder; Sani R. Nassif; Ulf Schlichtmann; Norbert Wehn (IEEE Micro, 2013)

Exploration and Optimization of 3-D Integrated DRAM Subsystems. - Christian Weis; Igor Loi; Luca Benini; Norbert Wehn (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Exploiting expendable process-margins in DRAMs for run-time performance optimization. - Karthik Chandrasekar 001; Sven Goossens; Christian Weis; Martijn Koedam; Benny Akesson; Norbert Wehn; Kees Goossens (DATE, 2014)

Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors. - Daniele Bortolotti; Andrea Bartolini; Christian Weis; Davide Rossi; Luca Benini (DATE, 2014)

Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh. - MohammadSadegh Sadri; Matthias Jung 001; Christian Weis; Norbert Wehn; Luca Benini (DATE, 2014)

Optimized active and power-down mode refresh control in 3D-DRAMs. - Matthias Jung 001; Christian Weis; Norbert Wehn; MohammadSadegh Sadri; Luca Benini (VLSI-SoC, 2014)

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. - Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit Kleeberger; Michael A. Kochte; Johannes Maximilian Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; et al. (Microelectron. Reliab., 2014)

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs. - Christian Weis; Matthias Jung 001; Peter Ehses; Cristiano Santos; Pascal Vivet; Sven Goossens; Martijn Koedam; Norbert Wehn (DATE, 2015)

A Custom Computing System for Finding Similarties in Complex Networks. - Christian Brugger; Valentin Grigorovici; Matthias Jung 001; Christian Weis; Christian de Schryver; Katharina Anna Zweig; Norbert Wehn (ISVLSI, 2015)

Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs. - Christian Weis; Matthias Jung 001; Omar Naji; Norbert Wehn; Cristiano Santos; Pascal Vivet; Andreas Hansson 001 (ISVLSI, 2015)

Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs. - Matthias Jung 001; Éder Zulian; Deepak M. Mathew; Matthias Herrmann; Christian Brugger; Christian Weis; Norbert Wehn (MEMSYS, 2015)

A high-level DRAM timing, power and area exploration tool. - Omar Naji; Christian Weis; Matthias Jung 001; Norbert Wehn; Andreas Hansson 001 (SAMOS, 2015)

DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework. - Matthias Jung 001; Christian Weis; Norbert Wehn (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

Application-aware cross-layer reliability analysis and optimization. - Michael Glaß; Hananeh Aliee; Liang Chen 014; Mojtaba Ebrahimi; Faramarz Khosravi; Veit B. Kleeberger; Alexandra Listl; Daniel Müller-Gritschneder; Fabian Oboril; Ulf Schlichtmann; Mehdi Baradaran Tahoori; Jürgen Teich; et al. (it Inf. Technol., 2015)

Efficient reliability management in SoCs - an approximate DRAM perspective. - Matthias Jung 001; Deepak M. Mathew; Christian Weis; Norbert Wehn (ASP-DAC, 2016)

Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM. - Matthias Jung 001; Deepak M. Mathew; Christian Weis; Norbert Wehn (DAC, 2016)

Error resilience and energy efficiency: An LDPC decoder design study. - Philipp Schläfer; Chu-Hsiang Huang; Clayton Schoeny; Christian Weis; Yao Li 007; Norbert Wehn; Lara Dolecek (DATE, 2016)

ConGen: An Application Specific DRAM Memory Controller Generator. - Matthias Jung 001; Deepak M. Mathew; Christian Weis; Norbert Wehn; Irene Heinrich; Marco V. Natale; Sven O. Krumke (MEMSYS, 2016)

Reverse Engineering of DRAMs: Row Hammer with Crosshair. - Matthias Jung 001; Carl Christian Rheinländer; Christian Weis; Norbert Wehn (MEMSYS, 2016)

A new bank sensitive DRAMPower model for efficient design space exploration. - Matthias Jung 001; Deepak M. Mathew; Éder F. Zulian; Christian Weis; Norbert Wehn (PATMOS, 2016)

A cross layer approach for efficient thermal management in 3D stacked SoCs. - Matthias Jung 001; Christian Weis; Norbert Wehn (Microelectron. Reliab., 2016)

An advanced embedded architecture for connected component analysis in industrial applications. - Menbere Tekleyohannes; MohammadSadegh Sadri; Christian Weis; Norbert Wehn; Martin Klein 005; Michael Siegrist (DATE, 2017)

Integrating DRAM power-down modes in gem5 and quantifying their impact. - Radhika Jagtap; Matthias Jung 001; Wendy Elsasser; Christian Weis; Andreas Hansson 001; Norbert Wehn (MEMSYS, 2017)

Using run-time reverse-engineering to optimize DRAM refresh. - Deepak M. Mathew; Éder F. Zulian; Matthias Jung 001; Kira Kraft; Christian Weis; Bruce L. Jacob; Norbert Wehn (MEMSYS, 2017)

A Bank-Wise DRAM Power Model for System Simulations. - Deepak M. Mathew; Éder F. Zulian; Subash Kannoth; Matthias Jung 001; Christian Weis; Norbert Wehn (RAPIDO, 2017)

A Platform to Analyze DDR3 DRAM's Power and Retention Time. - Matthias Jung 001; Deepak M. Mathew; Carl Christian Rheinländer; Christian Weis; Norbert Wehn (IEEE Des. Test, 2017)

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems. - Pei Liu 003; Ahmed Hemani; Kolin Paul; Christian Weis; Matthias Jung 001; Norbert Wehn (Int. J. Parallel Program., 2017)

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool. - Christian Weis; Abdul Mutaal; Omar Naji; Matthias Jung 001; Andreas Hansson 001; Norbert Wehn (Int. J. Parallel Program., 2017)

A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture. - Pei Liu 003; Ahmed Hemani; Kolin Paul; Christian Weis; Matthias Jung 001; Norbert Wehn (J. Signal Process. Syst., 2017)

Improving the error behavior of DRAM by exploiting its Z-channel property. - Kira Kraft; Chirag Sudarshan; Deepak M. Mathew; Christian Weis; Norbert Wehn; Matthias Jung 001 (DATE, 2018)

An analysis on retention error behavior and power consumption of recent DDR4 DRAMs. - Deepak M. Mathew; Martin Schultheis; Carl Christian Rheinländer; Chirag Sudarshan; Christian Weis; Norbert Wehn; Matthias Jung 001 (DATE, 2018)

A Reconfigurable Accelerator for Morphological Operations. - Menbere Kina Tekleyohannes; Christian Weis; Norbert Wehn; Martin Klein 005; Michael Siegrist (IPDPS Workshops, 2018)

The Role of Memories in Transprecision Computing. - Christian Weis; Matthias Jung 001; Éder F. Zulian; Chirag Sudarshan; Deepak M. Mathew; Norbert Wehn (ISCAS, 2018)

Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving. - Matthias Jung 001; Sally A. McKee; Chirag Sudarshan; Christoph Dropmann; Christian Weis; Norbert Wehn (MEMSYS, 2018)

Efficient coding scheme for DDR4 memory subsystems. - Kira Kraft; Deepak M. Mathew; Chirag Sudarshan; Matthias Jung 001; Christian Weis; Norbert Wehn; Florian Longnos (MEMSYS, 2018)

A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs. - Christian Brugger; Valentin Grigorovici; Matthias Jung 001; Christian de Schryver; Christian Weis; Norbert Wehn; Katharina Anna Zweig (IEEE Des. Test, 2018)

An In-DRAM Neural Network Processing Engine. - Chirag Sudarshan; Jan Lappas; Muhammad Mohsin Ghaffar; Vladimir Rybalkin; Christian Weis; Matthias Jung 001; Norbert Wehn (ISCAS, 2019)

Fast validation of DRAM protocols with timed petri nets. - Matthias Jung 001; Kira Kraft; Taha Soliman; Chirag Sudarshan; Christian Weis; Norbert Wehn (MEMSYS, 2019)

Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements. - Sven Müelich; Sebastian Bitzer; Chirag Sudarshan; Christian Weis; Norbert Wehn; Martin Bossert; Robert F. H. Fischer (REDUNDANCY, 2019)

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. - Deepak M. Mathew; André Lucas Chinazzo; Christian Weis; Matthias Jung 001; Bastien Giraud; Pascal Vivet; Alexandre Levisse; Norbert Wehn (SAMOS, 2019)

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing. - Chirag Sudarshan; Jan Lappas; Christian Weis; Deepak M. Mathew; Matthias Jung 001; Norbert Wehn (SAMOS, 2019)

eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. - Dimitrios Stathis 001; Chirag Sudarshan; Yu Yang; Matthias Jung 001; Syed Mohammad Asad Hassan Jafri; Christian Weis; Ahmed Hemani; Anders Lansner; Norbert Wehn (CoRR, 2019)

Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead. - Éder F. Zulian; Christian Weis; Norbert Wehn (ISCAS, 2020)

A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions. - Muhammad Mohsin Ghaffar; Chirag Sudarshan; Christian Weis; Matthias Jung 001; Norbert Wehn (MEMSYS, 2020)

An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices. - Deepak M. Mathew; Felipe S. Prado; Éder F. Zulian; Christian Weis; Muhammad Mohsin Ghaffar; Matthias Jung 001; Norbert Wehn (MEMSYS, 2020)

Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory. - Sven Müelich; Chirag Sudarshan; Christian Weis; Martin Bossert; Robert F. H. Fischer; Norbert Wehn (MEMSYS, 2020)

Efficient Generation of Application Specific Memory Controllers. - Marco V. Natale; Matthias Jung 001; Kira Kraft; Frederik Lauer; Johannes Feldmann; Chirag Sudarshan; Christian Weis; Sven Oliver Krumke; Norbert Wehn (MEMSYS, 2020)

System simulation with PULP virtual platform and SystemC. - Éder F. Zulian; Germain Haugou; Christian Weis; Matthias Jung 001; Norbert Wehn (RAPIDO, 2020)

The gem5 Simulator: Version 20.0+. - Jason Lowe-Power; Abdul Mutaal Ahmad; Ayaz Akram; Mohammad Alian; Rico Amslinger; Matteo Andreozzi; Adrià Armejach; Nils Asmussen; Srikant Bharadwaj; Gabe Black; Gedare Bloom; Bobby R. Bruce; et al. (CoRR, 2020)

Real-Time Energy Efficient Hand Pose Estimation: A Case Study. - Mhd Rashed Al Koutayni; Vladimir Rybalkin; Jameel Malik; Ahmed Elhayek; Christian Weis; Gerd Reis; Norbert Wehn; Didier Stricker (Sensors, 2020)

Efficient Hardware Architectures for 1D- and MD-LSTM Networks. - Vladimir Rybalkin; Chirag Sudarshan; Christian Weis; Jan Lappas; Norbert Wehn; Li Cheng (J. Signal Process. Syst., 2020)

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. - Dimitrios Stathis 001; Chirag Sudarshan; Yu Yang; Matthias Jung 001; Christian Weis; Ahmed Hemani; Anders Lansner; Norbert Wehn (J. Signal Process. Syst., 2020)

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. - Chirag Sudarshan; Taha Soliman; Cecilia De la Parra; Christian Weis; Leonardo Ecco; Matthias Jung 001; Norbert Wehn; Andre Guntoro (ASP-DAC, 2021)

The Dynamic Random Access Memory Challenge in Embedded Computing Systems. - Matthias Jung 001; Christian Weis; Norbert Wehn (A Journey of Embedded and Cyber-Physical Systems, 2021)

Burnt Forest Estimation from Sentinel-2 Imagery of Australia using Unsupervised Deep Learning. - Nosheen Abid; Muhammad Imran Malik; Muhammad Shahzad 002; Faisal Shafait; Haider Ali; Muhammad Mohsin Ghaffar; Christian Weis; Norbert Wehn; Marcus Liwicki (DICTA, 2021)

QuantYOLO: A High-Throughput and Power-Efficient Object Detection Network for Resource and Power Constrained UAVs. - Muhammad Gohar Javed; Minahil Raza; Muhammad Mohsin Ghaffar; Christian Weis; Norbert Wehn; Muhammad Shahzad 002; Faisal Shafait (DICTA, 2021)

Online Working Set Change Detection with Constant Complexity: The Cornerstone for Memory Management Algorithms in Scalable Systems. - L. J. Gokul Vasan; Éder F. Zulian; Christian Weis; Matthias Jung 001; Norbert Wehn (MEMSYS, 2021)

Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling. - Deepak M. Mathew; Hammam Kattan; Christian Weis; Jörg Henkel; Norbert Wehn; Hussam Amrouch (IEEE Access, 2021)

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation. - Chirag Sudarshan; Lukas Steiner; Matthias Jung 001; Jan Lappas; Christian Weis; Norbert Wehn (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks. - Vladimir Rybalkin; Chirag Sudarshan; Christian Weis; Jan Lappas; Norbert Wehn; Li Cheng (J. Signal Process. Syst., 2021)

Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node. - Jan Lappas; André Lucas Chinazzo; Christian Weis; Chenyang Xia; Zhihang Wu; Leibin Ni; Norbert Wehn (DATE, 2022)

Machine learning based soft error rate estimation of pass transistor logic in high-speed communication. - Zhe Zhang; Jan Lappas; André Lucas Chinazzo; Christian Weis; Zhihang Wu; Leibin Ni; Norbert Wehn; Mehdi B. Tahoori (ETS, 2022)

Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology. - André Lucas Chinazzo; Jan Lappas; Christian Weis; Qinhui Huang; Zhihang Wu; Leibin Ni; Norbert Wehn (ICECS 2022, 2022)

Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training. - Chirag Sudarshan; Mohammad Hassani Sadi; Christian Weis; Norbert Wehn (ISCAS, 2022)

A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions. - Chirag Sudarshan; Mohammad Hassani Sadi; Lukas Steiner; Christian Weis; Norbert Wehn (SAMOS, 2022)

FeFET versus DRAM based PIM Architectures: A Comparative Study. - Chirag Sudarshan; Taha Soliman; Thomas Kämpfe; Christian Weis; Norbert Wehn (VLSI-SoC, 2022)

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. - Chirag Sudarshan; Taha Soliman; Jan Lappas; Christian Weis; Mohammad Hassani Sadi; Matthias Jung 001; Andre Guntoro; Norbert Wehn (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. - Gia Bao Thieu; Sven Gesper; Guillermo Payá-Vayá; Christoph Riggers; Oliver Renke; Till Fiedler; Jakob Marten; Tobias Stuckenberg; Holger Blume; Christian Weis; Lukas Steiner; Chirag Sudarshan; et al. (DATE, 2023)

A Learning-Based Approach for Single Event Transient Analysis in Pass Transistor Logic. - Z. Zhang; Zhihang Wu; Christian Weis; Norbert Wehn; Mehdi Baradaran Tahoori (IOLTS, 2023)

The NWRD Dataset: An Open-Source Annotated Segmentation Dataset of Diseased Wheat Crop. - Hirra Anwar; Saad Ullah Khan 005; Muhammad Mohsin Ghaffar; Muhammad Fayyaz; Muhammad Jawad Khan; Christian Weis; Norbert Wehn; Faisal Shafait (Sensors, 2023)

Timing Analysis beyond Complementary CMOS Logic Styles. - Jan Lappas; Mohamed Amine Riahi; Christian Weis; Norbert Wehn; Sani R. Nassif (ASPDAC, 2024)

3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project. - Himar Fabelo; Raquel León; Emanuele Torti; Santiago Marco; Max Verbers; Yann Falevoz; Yolanda Ramallo-Fariña; Christian Weis; Ana M. Wägner; Eduardo Juárez Martínez; Claudio Rial; Alfonso Lagares; et al. (DSD, 2024)

Do Radiation and Aging Impact DVFS? TCAD-based Analysis on 22 nm FDSOI Latches. - Zhe Zhang; Christian Weis; Norbert Wehn; Mehdi B. Tahoori; Sani R. Nassif (IOLTS, 2024)

Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects. - Zhe Zhang; Mahta Mayahinia; Christian Weis; Norbert Wehn; Mehdi B. Tahoori; Sani R. Nassif; Grigor Tshagharyan; Gurgen Harutyunyan; Yervant Zorian (ITC, 2024)

A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces. - Mohammadreza Esmaeilpour; Jan Lappas; Hussien Abdo; Christian Weis; Norbert Wehn (NewCAS, 2024)

A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces. - Mohammadreza Esmaeilpour; Jan Lappas; Christian Weis; Norbert Wehn (NorCAS, 2024)

A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET Technology. - Mohammadreza Esmaeilpour; Jan Lappas; Christian Weis; Norbert Wehn (VLSI-SoC, 2024)

Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management. - Zhe Zhang; Mahta Mayahinia; Christian Weis; Norbert Wehn; Mehdi B. Tahoori; Sani R. Nassif; Grigor Tshagharyan; Gurgen Harutyunyan; Yervant Zorian (VTS, 2024)

Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables. - Hussien Abdo; Jan Lappas; Mohammadreza Esmaeilpour; Christian Weis; Norbert Wehn (DDECS, 2025)

Analysis and Mitigation of Radiation Effects in SRAM-based Register Files. - Zhe Zhang; Surendra Hemaram; Mahta Mayahinia; Christian Weis; Norbert Wehn; Mehdi B. Tahoori; Sani R. Nassif; Grigor Tshagharyan; Gurgen Harutyunyan; Yervant Zorian (ETS, 2025)

A 15 Gb/s Single-Ended Active-Inductive Equalizer with an Optimized Gain-Enhancing Technique. - Mohammadreza Esmaeilpour; Marco Mestice; Jan Lappas; Christian Weis; Norbert Wehn (NewCAS, 2025)

Enhanced LPDDR4X PHY in 12 nm FinFET. - Johannes Feldmann; Jan Lappas; Mohammadreza Esmaeilpour; Hussien Abdo; Christian Weis; Norbert Wehn (CoRR, 2025)