A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs. - Christoph Thomas Muller; Steffen Malkowsky; Oskar Andersson; Babak Mohammadi; Jens Sparsø; Joachim Neves Rodrigues (VLSI-SoC, 2013)

Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools. - Christoph Thomas Muller; Evangelia Kasapaki; Rasmus Bo Sørensen; Jens Sparsø (NORCHIP, 2014)

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation. - Evangelia Kasapaki; Martin Schoeberl; Rasmus Bo Sørensen; Christoph Thomas Muller; Kees Goossens; Jens Sparsø (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS. - Marc Pons 001; Christoph Thomas Müller; David Ruffieux; Jean-Luc Nagel; Stéphane Emery; Andreas Burg 001; Shuuji Tanahashi; Yoshitaka Tanaka; Atsushi Takeuchi (CICC, 2019)

Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC. - Christoph Thomas Müller; Marc Pons 001; David Ruffieux; Jean-Luc Nagel; Stéphane Emery; Andreas Burg 001; Shuuji Tanahashi; Yoshitaka Tanaka; Atsushi Takeuchi (PRIME, 2019)