6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters. - Christophe Erdmann; Donnacha Lowney; Adrian Lynam; Aidan Keady; John McGrath; Edward Cullen; Daire Breathnach; Denis Keane; Patrick Lynch; Marites De La Torre; Ronnie De La Torre; Peng Lim; et al. (ISSCC, 2014)

A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters. - Christophe Erdmann; Donnacha Lowney; Adrian Lynam; Aidan Keady; John McGrath; Edward Cullen; Daire Breathnach; Denis Keane; Patrick Lynch; Marites De La Torre; Ronnie De La Torre; Peng Lim; et al. (IEEE J. Solid State Circuits, 2015)

A programmable RFSoC in 16nm FinFET technology for wideband communications. - Brendan Farley; Christophe Erdmann; Bruno Vaz; John McGrath; Edward Cullen; Bob Verbruggen; Roberto Pelliconi; Daire Breathnach; Peng Lim; Ali Boumaalif; Patrick Lynch; Conrado Mesadri; et al. (A-SSCC, 2017)

16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz. - Christophe Erdmann; Edward Cullen; Damien Brouard; Roberto Pelliconi; Bob Verbruggen; John McGrath; Diarmuid Collins; Marites De La Torre; Pierrick Gay; Patrick Lynch; Peng Lim; Anthony Collins; et al. (ISSCC, 2017)

16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC. - Bruno Vaz; Adrian Lynam; Bob Verbruggen; Asma Laraba; Conrado Mesadri; Ali Boumaalif; John McGrath; Umanath Kamath; Ronnie De La Torre; Alvin Manlapat; Daire Breathnach; Christophe Erdmann; et al. (ISSCC, 2017)

A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. - Didem Turker; Ade Bekele; Parag Upadhyaya; Bob Verbruggen; Ying Cao 010; Shaojun Ma; Christophe Erdmann; Brendan Farley; Yohan Frans; Ken Chang (ISSCC, 2018)

A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC. - Christophe Erdmann; Bob Verbruggen; Bruno Vaz; Roberto Pelliconi; John McGrath; Ryan Kinnerk; Ronnie De La Torre; John O'Dwyer; Patrick Lynch; Padraig Kelly; Peng Lim; Daire Breathnach; et al. (VLSI Circuits, 2018)

A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET. - Bruno Vaz; Bob Verbruggen; Christophe Erdmann; Diarmuid Collins; John McGrath; Ali Boumaalif; Edward Cullen; Darragh Walsh; Alonso Morgado; Conrado Mesadri; Brian Long; Rajitha Pathepuram; et al. (VLSI Circuits, 2018)

An All-Programmable 16-nm RFSoC for Digital-RF Communications. - Brendan Farley; John McGrath; Christophe Erdmann (IEEE Micro, 2018)

A Wideband 6th Order Programmable Bandpass DEM Implementation for a Nyquist DAC. - Shantanu Mehta; Brendan Mullane; Vincent O'Brien; Roberto Pelliconi; Christophe Erdmann (ICECS, 2020)

A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters. - Shantanu Mehta; Brendan Mullane; Vincent O'Brien; Roberto Pelliconi; Christophe Erdmann (ISCAS, 2021)

Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters. - Shantanu Mehta; Roberto Pelliconi; Christophe Erdmann; Vincent O'Brien; Brendan Mullane (IEEE Open J. Circuits Syst., 2021)