Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI. - Kaya Can Akyel; Lorenzo Ciampolini; Olivier Thomas; Bertrand Pelloux-Prayer; Shishir Kumar; Philippe Flatresse; Christophe Lecocq; Gérard Ghibaudo (ISCAS, 2013)

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization. - David Jacquet; Frederic Hasbani; Philippe Flatresse; Robin Wilson; Franck Arnaud; Giorgio Cesana; Thierry Di Gilio; Christophe Lecocq; Tanmoy Roy; Amit Chhabra; Chiranjeev Grover; Olivier Minez; et al. (IEEE J. Solid State Circuits, 2014)

28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. - Rossella Ranica; Nicolas Planes; Vincent Huard; Olivier Weber; Daniel Noblet; Damien Croain; Fabien Giner; Sylvie Naudet; P. Mergault; S. Ibars; A. Villaret; Maryline Parra; et al. (VLSI Circuits, 2016)

40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode. - Kedar Janardan Dhori; Promod Kumar; Christophe Lecocq; Pascal Urard; Olivier Callen; Florian Cacho; Maryline Parra; Prashant Pandey; Daniel Noblet (VLSID, 2022)