Cache Refill/Access Decoupling for Vector Machines. - Christopher Batten; Ronny Krashinsky; Steve Gerding; Krste Asanovic (MICRO, 2004)

The Vector-Thread Architecture. - Ronny Krashinsky; Christopher Batten; Mark Hampton; Steve Gerding; Brian Pharris; Jared Casper; Krste Asanovic (IEEE Micro, 2004)

Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. - Christopher Batten; Ajay Joshi; Jason Orcutt; Anatoly Khilo; Benjamin Moss; Charles Holzwarth; Milos A. Popovic; Hanqing Li; Henry I. Smith; Judy L. Hoyt; Franz X. Kärtner; Rajeev J. Ram; et al. (Hot Interconnects, 2008)

Implementing the scale vector-thread processor. - Ronny Krashinsky; Christopher Batten; Krste Asanovic (ACM Trans. Design Autom. Electr. Syst., 2008)

Designing multi-socket systems using silicon photonics. - Scott Beamer; Krste Asanovic; Christopher Batten; Ajay Joshi; Vladimir Stojanovic (ICS, 2009)

Silicon-photonic clos networks for global on-chip communication. - Ajay Joshi; Christopher Batten; Yong-Jin Kwon; Scott Beamer; Imran Shamim; Krste Asanovic; Vladimir Stojanovic (NOCS, 2009)

Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics. - Christopher Batten; Ajay Joshi; Jason Orcutt; Anatol Khilo; Benjamin Moss; Charles Holzwarth; Milos A. Popovic; Hanqing Li; Henry I. Smith; Judy L. Hoyt; Franz X. Kärtner; Rajeev J. Ram; et al. (IEEE Micro, 2009)

Re-architecting DRAM memory systems with monolithically integrated silicon photonics. - Scott Beamer; Chen Sun 003; Yong-Jin Kwon; Ajay Joshi; Christopher Batten; Vladimir Stojanovic; Krste Asanovic (ISCA, 2010)

Simplified vector-thread architectures for flexible and efficient data-parallel accelerators. - Christopher Batten (2010)

The Maven vector-thread architecture. - Yunsup Lee; Rimas Avizienis; Alex Bishara; Richard Xia; Derek Lockhart; Christopher Batten; Krste Asanovic (Hot Chips Symposium, 2011)

Analysis of application-aware on-chip routing under traffic uncertainty. - Nithin Michael; Milen Nikolov; Ao Tang; G. Edward Suh; Christopher Batten (NOCS, 2011)

Designing Chip-Level Nanophotonic Interconnection Networks. - Christopher Batten; Ajay Joshi; Vladimir Stojanovic; Krste Asanovic (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Microarchitectural mechanisms to exploit value structure in SIMT architectures. - Ji Kim; Christopher Torng; Shreesha Srinath; Derek Lockhart; Christopher Batten (ISCA, 2013)

Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators. - Yunsup Lee; Rimas Avizienis; Alex Bishara; Richard Xia; Derek Lockhart; Christopher Batten; Krste Asanovic (ACM Trans. Comput. Syst., 2013)

Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks. - Waclaw Godycki; Christopher Torng; Ivan Bukreyev; Alyssa B. Apsel; Christopher Batten (MICRO, 2014)

Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists. - Ji Yun Kim; Christopher Batten (MICRO, 2014)

PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research. - Derek Lockhart; Gary Zibrat; Christopher Batten (MICRO, 2014)

Architectural Specialization for Inter-Iteration Loop Dependence Patterns. - Shreesha Srinath; Berkin Ilbeyi; Mingxing Tan; Gai Liu; Zhiru Zhang; Christopher Batten (MICRO, 2014)

Pydgin: generating fast instruction set simulators from simple architecture descriptions with meta-tracing JIT compilers. - Derek Lockhart; Berkin Ilbeyi; Christopher Batten (ISPASS, 2015)

Improving high-level synthesis with decoupled data structure optimization. - Ritchie Zhao; Gai Liu; Shreesha Srinath; Christopher Batten; Zhiru Zhang (DAC, 2016)

Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. - Christopher Torng; Moyang Wang; Bharath Sudheendra; Nagaraj Murali; Suren Jayasuriya; Shreesha Srinath; Taylor Pritchard; Robin Ying; Christopher Batten (Hot Chips Symposium, 2016)

Asymmetry-Aware Work-Stealing Runtimes. - Christopher Torng; Moyang Wang; Christopher Batten (ISCA, 2016)

JIT-assisted fast-forward embedding and instrumentation to enable fast, accurate, and agile simulation. - Berkin Ilbeyi; Christopher Batten (ISPASS, 2016)

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. - Steve Dai; Ritchie Zhao; Gai Liu; Shreesha Srinath; Udit Gupta; Christopher Batten; Zhiru Zhang (FPGA, 2017)

Cross-layer workload characterization of meta-tracing JIT VMs. - Berkin Ilbeyi; Carl Friedrich Bolz-Tereick; Christopher Batten (IISWC, 2017)

Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs. - Ji Kim; Shunning Jiang; Christopher Torng; Moyang Wang; Shreesha Srinath; Berkin Ilbeyi; Khalid Al-Hawaj; Christopher Batten (MICRO, 2017)

Mamba: closing the performance gap in productive hardware development frameworks. - Shunning Jiang; Berkin Ilbeyi; Christopher Batten (DAC, 2018)

An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware. - Tao Chen 045; Shreesha Srinath; Christopher Batten; G. Edward Suh (MICRO, 2018)

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. - Scott Davidson 004; Shaolin Xie; Christopher Torng; Khalid Al-Hawaj; Austin Rovinski; Tutu Ajayi; Luis Vega; Chun Zhao; Ritchie Zhao; Steve Dai; Aporva Amarnath; Bandhav Veluri; et al. (IEEE Micro, 2018)

Four Monolithically Integrated Switched-Capacitor DC-DC Converters With Dynamic Capacitance Sharing in 65-nm CMOS. - Ivan Bukreyev; Christopher Torng; Waclaw Godycki; Christopher Batten; Alyssa B. Apsel (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks. - Cheng Tan 002; Yanghui Ou; Shunning Jiang; Peitian Pan; Christopher Torng; Shady Agwa; Christopher Batten (ICCD, 2019)

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. - Austin Rovinski; Chun Zhao; Khalid Al-Hawaj; Paul Gao 001; Shaolin Xie; Christopher Torng; Scott Davidson 004; Aporva Amarnath; Luis Vega; Bandhav Veluri; Anuj Rao; Tutu Ajayi; et al. (VLSI Circuits, 2019)

Type freezing: exploiting attribute type monomorphism in tracing JIT compilers. - Lin Cheng; Berkin Ilbeyi; Carl Friedrich Bolz-Tereick; Christopher Batten (CGO, 2020)

Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems. - Moyang Wang; Tuan Ta; Lin Cheng; Christopher Batten (ISCA, 2020)

Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM. - Khalid Al-Hawaj; Olalekan Afuye; Shady Agwa; Alyssa B. Apsel; Christopher Batten (ISCAS, 2020)

Implementing Low-Diameter On-Chip Networks for Manycore Processors Using a Tiled Physical Design Methodology. - Yanghui Ou; Shady Agwa; Christopher Batten (NOCS, 2020)

PyMTL3: A Python Framework for Open-Source Hardware Modeling, Generation, Simulation, and Verification. - Shunning Jiang; Peitian Pan; Yanghui Ou; Christopher Batten (IEEE Micro, 2020)

UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling. - Shunning Jiang; Yanghui Ou; Peitian Pan; Christopher Batten (DAC, 2021)

Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM. - Olalekan Afuye; Shady Agwa; Christopher Batten; Alyssa B. Apsel (ESSDERC, 2021)

CAPE: A Content-Addressable Processing Engine. - Helena Caminal; Kailin Yang; Srivatsa Srinivasa; Akshay Krishna Ramanathan; Khalid Al-Hawaj; Tianshu Wu; Vijaykrishnan Narayanan; Christopher Batten; José F. Martínez (HPCA, 2021)

Ultra-Elastic CGRAs for Irregular Loop Specialization. - Christopher Torng; Peitian Pan; Yanghui Ou; Cheng Tan 002; Christopher Batten (HPCA, 2021)

PyH2: Using PyMTL3 to Create Productive and Open-Source Hardware Testing Methodologies. - Shunning Jiang; Yanghui Ou; Peitian Pan; Kaishuo Cheng; Yixiao Zhang; Christopher Batten (IEEE Des. Test, 2021)

big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip. - Tuan Ta; Khalid Al-Hawaj; Nick Cebry; Yanghui Ou; Eric Hall; Courtney Golden; Christopher Batten (MICRO, 2022)

A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. - Lin Cheng; Peitian Pan; Zhongyuan Zhao 004; Krithik Ranjan; Jack Weber; Bandhav Veluri; Seyed Borna Ehsani; Max Ruttenberg; Dai Cheol Jung; Preslav Ivanov; Dustin Richmond; Michael B. Taylor; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories. - Lin Cheng; Max Ruttenberg; Dai Cheol Jung; Dustin Richmond; Michael B. Taylor; Mark Oskin; Christopher Batten (ASPLOS (3), 2023)

CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. - Ting-Jung Chang; Ang Li 011; Fei Gao 016; Tuan Ta; Georgios Tziantzioulis; Yanghui Ou; Moyang Wang; Jinzheng Tu 001; Kaifeng Xu; Paul J. Jackson; August Ning; Grigory Chirkov; et al. (CICC, 2023)

EVE: Ephemeral Vector Engines. - Khalid Al-Hawaj; Tuan Ta; Nick Cebry; Shady Agwa; Olalekan Afuye; Eric Hall; Courtney Golden; Alyssa B. Apsel; Christopher Batten (HPCA, 2023)

Formal Verification of the Stall Invariant Property for Latency-Insensitive RTL Modules. - Peitian Pan; Christopher Batten (MEMOCODE, 2023)

Symbolic Elaboration: Checking Generator Properties in Dynamic Hardware Description Languages. - Peitian Pan; Shunning Jiang; Yanghui Ou; Christopher Batten (MEMOCODE, 2023)

GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment. - Max Doblas; Oscar Lostes-Cazorla; Quim Aguado-Puig; Nick Cebry; Pau Fontova-Musté; Christopher Frances Batten; Santiago Marco-Sola; Miquel Moretó (MICRO, 2023)

NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. - Matthew Guthaus; Christopher Batten; Erik Brunvand; Pierre-Emmanuel Gaillardon; David M. Harris; Rajit Manohar; Pinaki Mazumder; Larry T. Pileggi; James E. Stine (CoRR, 2023)

Special Issue on Top Picks From the 2022 Computer Architecture Conferences. - Christopher Batten; Jae W. Lee (IEEE Micro, 2023)

Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. - Dai Cheol Jung; Max Ruttenberg; Paul Gao 001; Scott Davidson 004; Daniel Petrisko; Kangli Li; Aditya K. Kamath; Lin Cheng; Shaolin Xie; Peitian Pan; Zhongyuan Zhao 004; Zichao Yue; et al. (ISCA, 2024)

PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs. - Christopher Batten; Nathaniel Ross Pinckney; Mingjie Liu; Haoxing Ren; Brucek Khailany (MLCAD, 2024)

Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator. - Courtney Golden; Dan Ilan; Caroline Huang; Niansong Zhang; Zhiru Zhang; Christopher Batten (IEEE Comput. Archit. Lett., 2024)

Accelerating Seed Location Filtering in DNA Read Mapping Using a Commercial Compute-in-SRAM Architecture. - Courtney Golden; Dan Ilan; Nicholas Cebry; Christopher Batten (CoRR, 2024)

Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks. - Nathaniel Ross Pinckney; Christopher Batten; Mingjie Liu; Haoxing Ren; Brucek Khailany (CoRR, 2024)

Scaling Co-Packaged Optical Interconnects Using Hybrid 2.5D/3D Integration. - Austin Rovinski; Yanghui Ou; Christine Ou; Devesh Khilwani; Yuyang Wang 003; Songli Wang; Sunwoo Lee 002; Keren Bergman; Alyosha C. Molnar; Christopher Batten (ISCAS, 2025)

Optically Connected Multi-Stack HBM Modules for Large Language Model Training and Inference. - Yanghui Ou; Hengrui Zhang; Austin Rovinski; David Wentzlaff; Christopher Batten (IEEE Comput. Archit. Lett., 2025)

SparseZipper: Enhancing Matrix Extensions to Accelerate SpGEMM on CPUs. - Tuan Ta; Joshua Randall 001; Christopher Batten (CoRR, 2025)