Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry. - Jim Le; Christopher Hanken; Martin Held; Michael S. Hagedorn; Kartikeya Mayaram; Terri S. Fiez (CICC, 2006)

Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits. - Christopher Hanken; Jim Le; Terri S. Fiez; Kartikeya Mayaram (CICC, 2007)

Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes. - Wai Leng Cheong; Brian E. Owens; Hui En Pham; Christopher Hanken; Jim Le; Terri S. Fiez; Kartikeya Mayaram (ISQED, 2009)

Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. - Jim Le; Christopher Hanken; Martin Held; Michael S. Hagedorn; Kartikeya Mayaram; Terri S. Fiez (IEEE Trans. Very Large Scale Integr. Syst., 2012)