SMOS: A CAD-compatible statistical model for analogue mos integrated circuit simulation. - Christopher Michael; Christopher J. Abel; Mohammed Ismail 001 (Int. J. Circuit Theory Appl., 1992)

A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits. - Christopher Michael; Christopher J. Abel; C. S. Teng (ICCAD, 1993)

Characterization of Transistor Mismatch for Statistical CAD of Submicron CMOS Analog Circuits. - Christopher J. Abel; Christopher Michael; Mohammed Ismail 001; C. S. Teng; R. Lahrio (ISCAS, 1993)

Four-Quadrant CMOS/BiCMOS Multipliers Using Linear-Region MOS Transistors. - Christopher J. Abel; Satoshi Sakurai; Frode Larsen; Mohammed Ismail 001 (ISCAS, 1994)

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS. - Hiroshi Kimura; Pervez M. Aziz; Tai Jing; Ashutosh Sinha; Ram Narayan; Hairong Gao; Ping Jing; Gary Hom; Anshi Liang; Eric Zhang; Aniket Kadkol; Ruchi Kothari; et al. (ISSCC, 2014)

A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS. - Hiroshi Kimura; Pervez M. Aziz; Tai Jing; Ashutosh Sinha; Shiva Prasad Kotagiri; Ram Narayan; Hairong Gao; Ping Jing; Gary Hom; Anshi Liang; Eric Zhang; Aniket Kadkol; et al. (IEEE J. Solid State Circuits, 2014)