Speculative precomputation: long-range prefetching of delinquent loads. - Jamison D. Collins; Hong Wang 003; Dean M. Tullsen; Christopher J. Hughes; Yong-Fong Lee; Daniel M. Lavery; John Paul Shen (ISCA, 2001)

Variability in the execution of multimedia applications and implications for architecture. - Christopher J. Hughes; Praful Kaul; Sarita V. Adve; Rohit Jain; Chanik Park; Jayanth Srinivasan (ISCA, 2001)

Saving energy with architectural and frequency adaptations for multimedia applications. - Christopher J. Hughes; Jayanth Srinivasan; Sarita V. Adve (MICRO, 2001)

Joint local and global hardware adaptations for energy. - Ruchira Sasanka; Christopher J. Hughes; Sarita V. Adve (ASPLOS, 2002)

Soft Real- Time Scheduling on Simultaneous Multithreaded Processors. - Rohit Jain; Christopher J. Hughes; Sarita V. Adve (RTSS, 2002)

RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors. - Christopher J. Hughes; Vijay S. Pai; Parthasarathy Ranganathan; Sarita V. Adve (Computer, 2002)

General -Purpose Processors for Multimedia Applications: Predictability and Energy Efficiency - Christopher J. Hughes (2003)

A Formal Approach to Frequent Energy Adaptations for Multimedia Applications. - Christopher J. Hughes; Sarita V. Adve (ISCA, 2004)

Memory-side prefetching for linked data structures for processor-in-memory systems. - Christopher J. Hughes; Sarita V. Adve (J. Parallel Distributed Comput., 2005)

Incremental approximate matrix factorization for speeding up support vector machines. - Gang Wu 005; Edward Y. Chang; Yen-Kuang Chen; Christopher J. Hughes (KDD, 2006)

Hybrid transactional memory. - Sanjeev Kumar; Michael Chu; Christopher J. Hughes; Partha Kundu; Anthony D. Nguyen (PPoPP, 2006)

Computer Vision on Multi-Core Processors: Articulated Body Tracking. - Trista Pei-Chun Chen; Dmitry Budnikov; Christopher J. Hughes; Yen-Kuang Chen (ICME, 2007)

Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. - Christopher J. Hughes; Radek Grzeszczuk; Eftychios Sifakis; Daehyun Kim 001; Sanjeev Kumar; Andrew Selle; Jatin Chhugani; Matthew J. Holliman; Yen-Kuang Chen (ISCA, 2007)

Carbon: architectural support for fine-grained parallelism on chip multiprocessors. - Sanjeev Kumar; Christopher J. Hughes; Anthony D. Nguyen (ISCA, 2007)

Atomic Vector Operations on Chip Multiprocessors. - Sanjeev Kumar; Daehyun Kim 001; Mikhail Smelyanskiy; Yen-Kuang Chen; Jatin Chhugani; Christopher J. Hughes; Changkyu Kim; Victor W. Lee; Anthony D. Nguyen (ISCA, 2008)

Convergence of Recognition, Mining, and Synthesis Workloads and Its Implications. - Yen-Kuang Chen; Jatin Chhugani; Pradeep Dubey; Christopher J. Hughes; Daehyun Kim 001; Sanjeev Kumar; Victor W. Lee; Anthony D. Nguyen; Mikhail Smelyanskiy (Proc. IEEE, 2008)

Scalable HMM based inference engine in large vocabulary continuous speech recognition. - Jike Chong; Kisun You; Youngmin Yi; Ekaterina Gonina; Christopher J. Hughes; Wonyong Sung; Kurt Keutzer (ICME, 2009)

Parallel scalability in speech recognition. - Kisun You; Jike Chong; Youngmin Yi; Ekaterina Gonina; Christopher J. Hughes; Yen-Kuang Chen; Wonyong Sung; Kurt Keutzer (IEEE Signal Process. Mag., 2009)

Performance and Energy Implications of Many-Core Caches for Throughput Computing. - Christopher J. Hughes; Changkyu Kim; Yen-Kuang Chen (IEEE Micro, 2010)

LIME: a framework for debugging load imbalance in multi-threaded execution. - Jungju Oh; Christopher J. Hughes; Guru Venkataramani; Milos Prvulovic (ICSE, 2011)

Moguls: a model to explore the memory hierarchy for bandwidth improvements. - Guangyu Sun 003; Christopher J. Hughes; Changkyu Kim; Jishen Zhao; Cong Xu 002; Yuan Xie 001; Yen-Kuang Chen (ISCA, 2011)

DeFT: Design space exploration for on-the-fly detection of coherence misses. - Guru Venkataramani; Christopher J. Hughes; Sanjeev Kumar; Milos Prvulovic (ACM Trans. Archit. Code Optim., 2011)

Exploring SIMD for Molecular Dynamics, Using Intel® Xeon® Processors and Intel® Xeon Phi Coprocessors. - Simon J. Pennycook; Christopher J. Hughes; Mikhail Smelyanskiy; Stephen A. Jarvis (IPDPS, 2013)

Location-aware cache management for many-core processors with deep cache hierarchy. - Jongsoo Park; Richard M. Yoo; Daya Shanker Khudia; Christopher J. Hughes; Daehyun Kim 001 (SC, 2013)

Performance evaluation of Intel® transactional synchronization extensions for high-performance computing. - Richard M. Yoo; Christopher J. Hughes; Konrad Lai; Ravi Rajwar (SC, 2013)

Locality-aware task management for unstructured parallelism: a quantitative limit study. - Richard M. Yoo; Christopher J. Hughes; Changkyu Kim; Yen-Kuang Chen; Christos Kozyrakis (SPAA, 2013)

IMP: indirect memory prefetcher. - Xiangyao Yu; Christopher J. Hughes; Nadathur Satish; Srinivas Devadas (MICRO, 2015)

Single-Instruction Multiple-Data Execution - Christopher J. Hughes (Morgan & Claypool Publishers, 2015)

PleaseTM: Enabling transaction conflict management in requester-wins hardware transactional memory. - Sunjae Park; Milos Prvulovic; Christopher J. Hughes (HPCA, 2016)

Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation. - Xiangyao Yu; Christopher J. Hughes; Nadathur Satish; Onur Mutlu; Srinivas Devadas (MICRO, 2017)

Transactional pre-abort handlers in hardware transactional memory. - Sunjae Park; Christopher J. Hughes; Milos Prvulovic (PACT, 2018)

Dynamic fine-grained sparse memory accesses. - Berkin Akin; Chiachen Chou; Jongsoo Park; Christopher J. Hughes; Rajat Agarwal (MEMSYS, 2018)

Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory. - Sunjae Park; Christopher J. Hughes; Milos Prvulovic (PACT, 2019)

T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations. - Nitish Kumar Srivastava; Hongbo Rong; Prithayan Barua; Guanyu Feng; Huanqi Cao; Zhiru Zhang; David H. Albonesi; Vivek Sarkar; Wenguang Chen; Paul Petersen; Geoff Lowney; Adam Herr; et al. (FCCM, 2019)

SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (CoRR, 2019)

SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (PACT, 2020)

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. - Yi-Hsiang Lai; Hongbo Rong; Size Zheng 001; Weihao Zhang; Xiuping Cui; Yunshan Jia; Jie Wang 022; Brendan Sullivan; Zhiru Zhang; Yun Liang 001; Youhui Zhang; Jason Cong; et al. (ICCAD, 2020)

SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Sara S. Baghsorkhi; Josep Torrellas (MICRO, 2020)

RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. - Geonhwa Jeong; Eric Qin 001; Ananda Samajdar; Christopher J. Hughes; Sreenivas Subramoney; Hyesoon Kim; Tushar Krishna (DAC, 2021)

SumMerge: an efficient algorithm and implementation for weight repetition-aware DNN inference. - Rohan Baskar Prabhakar; Sachit Kuhar; Rohit Agrawal 001; Christopher J. Hughes; Christopher W. Fletcher (ICS, 2021)

Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques. - Zhangxiaowen Gong; Houxiang Ji; Yao Yao; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (ISCA, 2022)

VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. - Geonhwa Jeong; Sana Damani; Abhimanyu Rajeshkumar Bambhaniya; Eric Qin 001; Christopher J. Hughes; Sreenivas Subramoney; Hyesoon Kim; Tushar Krishna (HPCA, 2023)

M3XU: Achieving High-Precision and Complex Matrix Multiplication with Low-Precision MXUs. - Dongho Ha; Yunan Zhang; Chen-Chien Kao; Christopher J. Hughes; Won Woo Ro; Hung-Wei Tseng 001 (SC, 2024)

Push Multicast: A Speculative and Coherent Interconnect for Mitigating Manycore CPU Communication Bottleneck. - Jiayi Huang 001; Yanhua Chen; Zhe Wang 023; Christopher J. Hughes; Yufei Ding 001; Yuan Xie 001 (HPCA, 2025)