A single-chip universal digital satellite receiver with 480-MHz IF input. - Alan Y. Kwentus; Patrick Pai; Steven Jaffe; Ray Gomez; Shauhyuarn Sean Tsai; Tom Kwan; Hing T. Hung; Young J. Shin; Vin Hue; Darwin Cheung; Raheel A. Khan; Christopher M. Ward; et al. (IEEE J. Solid State Circuits, 1999)

A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-μm CMOS. - Jan Mulder; Christopher M. Ward; Chi-Hung Lin; David Kruse; Jan R. Westra; Marcel Lugthart; Erol Arslan; Rudy J. van de Plassche; Klaas Bult; Frank M. L. van der Goes (IEEE J. Solid State Circuits, 2004)

An 800MS/s dual-residue pipeline ADC in 40nm CMOS. - Jan Mulder; Frank M. L. van der Goes; Davide Vecchi; Jan R. Westra; Emre Ayranci; Christopher M. Ward; Jiansong Wan; Klaas Bult (ISSCC, 2011)

An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS. - Davide Vecchi; Jan Mulder; Frank M. L. van der Goes; Jan R. Westra; Emre Ayranci; Christopher M. Ward; Jiansong Wan; Klaas Bult (IEEE J. Solid State Circuits, 2011)

11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS. - Frank M. L. van der Goes; Christopher M. Ward; Santosh Astgimath; Han Yan; Jeff Riley; Jan Mulder; Sijia Wang; Klaas Bult (ISSCC, 2014)

A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS. - Frank M. L. van der Goes; Christopher M. Ward; Santosh Astgimath; Han Yan; Jeff Riley; Zeng Zeng; Jan Mulder; Sijia Wang; Klaas Bult (IEEE J. Solid State Circuits, 2014)

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS. - Jan Mulder; Davide Vecchi; Yi Ke; Stefano Bozzola; Mark Core; Nitz Saputra; Qiongna Zhang; Jeff Riley; Han Yan; Mattia Introini; Sijia Wang; Christopher M. Ward; et al. (ISSCC, 2015)

ngsReports: a Bioconductor package for managing FastQC reports and other NGS related log files. - Christopher M. Ward; Thu-Hien To; Stephen M. Pederson (Bioinform., 2020)