Ultralow-power SRAM technology. - Randy W. Mann; W. W. (Bill) Abadeer; Matthew J. Breitwisch; O. Bula; Jeff S. Brown; Bryant C. Colwill; Peter E. Cottrell; William T. Crocco Jr.; Stephen S. Furkay; Michael J. Hauser; Terence B. Hook; Dennis Hoyniak; et al. (IBM J. Res. Dev., 2003)

Gate stack resistance and limits to CMOS logic performance. - Richard A. Wachnik; Sungjae Lee 005; Li-Hong Pan; Ning Lu; Hongmei Li; Raphael Bingert; Mai Randall; Scott K. Springer; Christopher S. Putnam (CICC, 2013)

Gate Stack Resistance and Limits to CMOS Logic Performance. - Richard A. Wachnik; Sungjae Lee 005; Li-Hong Pan; Hongmei Li; Ning Lu; Jing Wang; Christophe Bernicot; Raphael Bingert; Mai Randall; Scott K. Springer; Christopher S. Putnam (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)