Efficient checker processor design. - Saugata Chatterjee; Christopher T. Weaver; Todd M. Austin (MICRO, 2000)

Application specific architectures: a recipe for fast, flexible and power efficient designs. - Christopher T. Weaver; Rajeev Krishna; Lisa Wu 001; Todd M. Austin (CASES, 2001)

Scalable Hybrid Verification of Complex Microprocessors. - Maher N. Mneimneh; Fadi A. Aloul; Christopher T. Weaver; Saugata Chatterjee; Karem A. Sakallah; Todd M. Austin (DAC, 2001)

A Fault Tolerant Approach to Microprocessor Design. - Christopher T. Weaver; Todd M. Austin (DSN, 2001)

CryptoManiac: a fast flexible architecture for secure communication. - Lisa Wu 001; Christopher T. Weaver; Todd M. Austin (ISCA, 2001)

Performance analysis using pipeline visualization. - Christopher T. Weaver; Kenneth C. Barr; Eric D. Marsman; Dan Ernst; Todd M. Austin (ISPASS, 2001)

Effective support of simulation in computer architecture instruction. - Christopher T. Weaver; Eric Larson; Todd M. Austin (WCAE, 2002)

A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. - Shubhendu S. Mukherjee; Christopher T. Weaver; Joel S. Emer; Steven K. Reinhardt; Todd M. Austin (MICRO, 2003)

Measuring Architectural Vulnerability Factors. - Shubhendu S. Mukherjee; Christopher T. Weaver; Joel S. Emer; Steven K. Reinhardt; Todd M. Austin (IEEE Micro, 2003)

Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. - Christopher T. Weaver; Joel S. Emer; Shubhendu S. Mukherjee; Steven K. Reinhardt (ISCA, 2004)

Reducing the Soft-Error Rate of a High-Performance Microprocessor. - Christopher T. Weaver; Joel S. Emer; Shubhendu S. Mukherjee; Steven K. Reinhardt (IEEE Micro, 2004)

Intel® atomTM processor core made FPGA-synthesizable. - Perry H. Wang; Jamison D. Collins; Christopher T. Weaver; Belliappa Kuttanna; Shahram Salamian; Gautham N. Chinya; Ethan Schuchman; Oliver Schilling; Thorsten Doil; Sebastian Steibl; Hong Wang 003 (FPGA, 2009)

Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture. - Guilherme Ottoni; Thomas Hartin; Christopher T. Weaver; Jason Brandt; Belliappa Kuttanna; Hong Wang 003 (Conf. Computing Frontiers, 2011)