Microarchitectural mechanisms to exploit value structure in SIMT architectures. - Ji Kim; Christopher Torng; Shreesha Srinath; Derek Lockhart; Christopher Batten (ISCA, 2013)

Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks. - Waclaw Godycki; Christopher Torng; Ivan Bukreyev; Alyssa B. Apsel; Christopher Batten (MICRO, 2014)

Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. - Christopher Torng; Moyang Wang; Bharath Sudheendra; Nagaraj Murali; Suren Jayasuriya; Shreesha Srinath; Taylor Pritchard; Robin Ying; Christopher Batten (Hot Chips Symposium, 2016)

Asymmetry-Aware Work-Stealing Runtimes. - Christopher Torng; Moyang Wang; Christopher Batten (ISCA, 2016)

Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs. - Ji Kim; Shunning Jiang; Christopher Torng; Moyang Wang; Shreesha Srinath; Berkin Ilbeyi; Khalid Al-Hawaj; Christopher Batten (MICRO, 2017)

A modular digital VLSI flow for high-productivity SoC design. - Brucek Khailany; Evgeni Khmer; Rangharajan Venkatesan; Jason Clemons; Joel S. Emer; Matthew Fojtik; Alicia Klinefelter; Michael Pellauer; Nathaniel Ross Pinckney; Yakun Sophia Shao; Shreesha Srinath; Christopher Torng; et al. (DAC, 2018)

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. - Scott Davidson 004; Shaolin Xie; Christopher Torng; Khalid Al-Hawaj; Austin Rovinski; Tutu Ajayi; Luis Vega; Chun Zhao; Ritchie Zhao; Steve Dai; Aporva Amarnath; Bandhav Veluri; et al. (IEEE Micro, 2018)

Four Monolithically Integrated Switched-Capacitor DC-DC Converters With Dynamic Capacitance Sharing in 65-nm CMOS. - Ivan Bukreyev; Christopher Torng; Waclaw Godycki; Christopher Batten; Alyssa B. Apsel (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks. - Cheng Tan 002; Yanghui Ou; Shunning Jiang; Peitian Pan; Christopher Torng; Shady Agwa; Christopher Batten (ICCD, 2019)

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. - Austin Rovinski; Chun Zhao; Khalid Al-Hawaj; Paul Gao 001; Shaolin Xie; Christopher Torng; Scott Davidson 004; Aporva Amarnath; Luis Vega; Bandhav Veluri; Anuj Rao; Tutu Ajayi; et al. (VLSI Circuits, 2019)

Creating an Agile Hardware Design Flow. - Rick Bahr; Clark W. Barrett; Nikhil Bhagdikar; Alex Carsello; Ross Daly; Caleb Donovick; David Durst; Kayvon Fatahalian; Kathleen Feng; Pat Hanrahan; Teguh Hofstee; Mark Horowitz; et al. (DAC, 2020)

Ultra-Elastic CGRAs for Irregular Loop Specialization. - Christopher Torng; Peitian Pan; Yanghui Ou; Cheng Tan 002; Christopher Batten (HPCA, 2021)

Enabling Reusable Physical Design Flows with Modular Flow Generators. - Alex Carsello; James Thomas 003; Ankita Nayak; Po-Han Chen; Mark Horowitz; Priyanka Raina; Christopher Torng (CoRR, 2021)

Fast Extended GCD Calculation for Large Integers for Verifiable Delay Functions. - Kavya Sreedhar; Mark Horowitz; Christopher Torng (IACR Cryptol. ePrint Arch., 2021)

mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited. - Alex Carsello; James Thomas 003; Ankita Nayak; Po-Han Chen; Mark Horowitz; Priyanka Raina; Christopher Torng (DAC, 2022)

Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration. - Kathleen Feng; Alex Carsello; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (HCS, 2022)

Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Alex Carsello; Kathleen Feng; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (VLSI Technology and Circuits, 2022)

A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion. - Kavya Sreedhar; Mark Horowitz; Christopher Torng (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

Building First-Order Energy Modeling Intuition in Computer Architecture Lectures. - Christopher Torng (WCAE, 2023)

Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays. - Jackson Melchert; Keyi Zhang; Yuchen Mei; Mark Horowitz; Christopher Torng; Priyanka Raina (IEEE Comput. Archit. Lett., 2023)

Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays. - Taeyoung Kong; Kalhan Koul; Priyanka Raina; Mark Horowitz; Christopher Torng (CoRR, 2023)

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers. - Kalhan Koul; Jackson Melchert; Kavya Sreedhar; Leonard Truong; Gedeon Nyengele; Keyi Zhang; Qiaoyi Liu; Jeff Setter; Po-Han Chen; Yuchen Mei; Maxwell Strange; Ross Daly; et al. (ACM Trans. Embed. Comput. Syst., 2023)

Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains. - Ankita Nayak; Keyi Zhang; Rajsekhar Setaluri; Alex Carsello; Makai Mann; Christopher Torng; Stephen Richardson; Rick Bahr; Pat Hanrahan; Mark Horowitz; Priyanka Raina (ACM Trans. Reconfigurable Technol. Syst., 2023)

Onyx: A Programmable Accelerator for Sparse Tensor Algebra. - Kalhan Koul; Maxwell Strange; Jackson Melchert; Alex Carsello; Yuchen Mei; Olivia Hsu; Taeyoung Kong; Po-Han Chen; Huifeng Ke; Keyi Zhang; Qiaoyi Liu; Gedeon Nyengele; et al. (HCS, 2024)

Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications. - Kalhan Koul; Maxwell Strange; Jackson Melchert; Alex Carsello; Yuchen Mei; Olivia Hsu; Taeyoung Kong; Po-Han Chen; Huifeng Ke; Keyi Zhang; Qiaoyi Liu; Gedeon Nyengele; et al. (VLSI Technology and Circuits, 2024)

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Kathleen Feng; Taeyoung Kong; Kalhan Koul; Jackson Melchert; Alex Carsello; Qiaoyi Liu; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (IEEE J. Solid State Circuits, 2024)