Implementing asynchronous circuits using a conventional EDA tool-flow. - Christos P. Sotiriou (DAC, 2002)

Read, use, simulate, experiment and build: an integrated approach for teaching computer architecture. - Ioannis Papaefstathiou; Christos P. Sotiriou (WCAE, 2002)

Automating the design of an asynchronous DLX microprocessor. - Manish Amde; Ivan Blunno; Christos P. Sotiriou (DAC, 2003)

Design-space exploration of a cryptography algorithm. - Christos P. Sotiriou; Ioannis Papaefstathiou (ICECS, 2003)

Handshake Protocols for De-Synchronization. - Ivan Blunno; Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Kelvin Lwin; Christos P. Sotiriou (ASYNC, 2004)

Data Synchronization Issues in GALS SoCs. - Rostislav (Reuven) Dobkin; Ran Ginosar; Christos P. Sotiriou (ASYNC, 2004)

From Synchronous to Asynchronous: An Automatic Approach. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Kelvin Lwin; Christos P. Sotiriou (DATE, 2004)

Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. - Aristides Efthymiou; Christos P. Sotiriou; Douglas A. Edwards (DATE, 2004)

Coping with The Variability of Combinational Logic Delays. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Christos P. Sotiriou (ICCD, 2004)

Design-space exploration of the most widely used cryptography algorithms. - Ioannis Papaefstathiou; Vassilis Papaefstathiou; Christos P. Sotiriou (Microprocess. Microsystems, 2004)

Controlling Event Spacing in Self-Timed Rings. - Vassilis Zebilis; Christos P. Sotiriou (ASYNC, 2005)

Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. - Evangelia Kassapaki; Pavlos M. Mattheakis; Christos P. Sotiriou (FPL, 2006)

Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. - Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Christos P. Sotiriou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

High Rate Data Synchronization in GALS SoCs. - Rostislav (Reuven) Dobkin; Ran Ginosar; Christos P. Sotiriou (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A Fully-Automated Desynchronization Flow for Synchronous Circuits. - Nikolaos Andrikos; Luciano Lavagno; Davide Pandini; Christos P. Sotiriou (DAC, 2007)

A comparative study of survival models for breast cancer prognostication based on microarray data: does a single gene beat them all? - Benjamin Haibe-Kains; Christine Desmedt; Christos P. Sotiriou; Gianluca Bontempi (Bioinform., 2008)

Computational Intelligence in Clinical Oncology: Lessons Learned from an Analysis of a Clinical Study. - Benjamin Haibe-Kains; Christine Desmedt; Sherene Loi; Mauro Delorenzi; Christos P. Sotiriou; Gianluca Bontempi (Computational Intelligence in Biomedicine and Bioinformatics, 2008)

CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits. - Evriklis Kounalakis; Christos P. Sotiriou (ASYNC, 2011)

SCPlace: A statistical slack-assignment based constructive placer. - Evriklis Kounalakis; Christos P. Sotiriou (ISQED, 2011)

Statistical Timing-Based Post-Placement Leakage Recovery. - Evriklis Kounalakis; Christos P. Sotiriou; Vassilis Zebilis (ISVLSI, 2011)

Multiple-input multiple-output causal strategies for gene selection. - Gianluca Bontempi; Benjamin Haibe-Kains; Christine Desmedt; Christos P. Sotiriou; John Quackenbush (BMC Bioinform., 2011)

Consistent metagenes from cancer expression profiles yield agent specific predictors of chemotherapy response. - Qiyuan Li; Aron C. Eklund; Nicolai J. Birkbak; Christine Desmedt; Benjamin Haibe-Kains; Christos P. Sotiriou; W. Fraser Symmans; Lajos Pusztai; Søren Brunak; Andrea L. Richardson; Zoltan Szallasi (BMC Bioinform., 2011)

A polynomial time flow for implementing free-choice Petri-nets. - Pavlos M. Mattheakis; Christos P. Sotiriou; Peter A. Beerel (ICCD, 2012)

Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition. - Pavlos M. Mattheakis; Christos P. Sotiriou (VLSI Design, 2013)

Low Power Monolithic 3D IC Design of Asynchronous AES Core. - Neela Lohith Penmetsa; Christos P. Sotiriou; Sung Kyu Lim (ASYNC, 2015)

Asynchronous sub-threshold ultra-low power processor. - Ron Diamant; Ran Ginosar; Christos P. Sotiriou (PATMOS, 2015)

Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategies. - Nikolaos Sketopoulos; Christos P. Sotiriou; Stavros Simoglou (DATE, 2018)

Investigation and Trade-offs in 3DIC Partitioning Methodologies: N/A. - Nikolaos Sketopoulos; Christos P. Sotiriou; Vasileios Samaras (ACM Great Lakes Symposium on VLSI, 2019)

Timing Errors in STA-based Gate-Level Simulation. - Stavros Simoglou; Christos P. Sotiriou; Nikolaos Blias (ASYNC, 2020)

Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL. - Christos Georgakidis; Christos P. Sotiriou (DFT, 2020)

A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic. - Christos Georgakidis; Georgios Ioannis Paliaroutis; Nikolaos Sketopoulos; Pelopidas Tsoumanis; Christos P. Sotiriou; Nestor E. Evmorfopoulos; Georgios I. Stamoulis (ISQED, 2020)

R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints. - Christos Georgakidis; Christos P. Sotiriou; Nikolaos Sketopoulos; Milos Krstic; Oliver Schrape; Anselm Breitenreiter (ISVLSI, 2020)

STA for Mixed Cyclic, Acyclic Circuits. - Stavros Simoglou; Christos P. Sotiriou; Dimitris Valiantzas; Nikolaos Sketopoulos (ISVLSI, 2020)

Metal Stack and Partitioning Exploration for Monolithic 3D ICs. - Nikolaos Sketopoulos; Christos P. Sotiriou; Vasilis F. Pavlidis (ISVLSI, 2020)

Graph-based STA for asynchronous controllers. - Stavros Simoglou; Nikolaos Xiromeritis; Christos P. Sotiriou; Nikolaos Sketopoulos (Integr., 2020)

RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints. - Christos Georgakidis; Iordanis Lilitsis; Georgios Stanimeropoulos; Christos P. Sotiriou (DFT, 2021)

Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits. - Stavros Simoglou; Christos P. Sotiriou; Nikolaos Blias (DFT, 2021)

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs. - Osama Bin Tariq; Junnan Shan; Georgios Floros 002; Christos P. Sotiriou; Mario R. Casu; Mihai Teodor Lazarescu; Luciano Lavagno (IEEE Access, 2021)

Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits. - Kimia Zamiri Azar; Hadi Mardani Kamali; Shervin Roshanisefat; Houman Homayoun; Christos P. Sotiriou; Avesta Sasan (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance. - Dimitrios Garyfallou; Stavros Simoglou; Nikolaos Sketopoulos; Charalampos Antoniadis; Christos P. Sotiriou; Nestor E. Evmorfopoulos; George I. Stamoulis (IEEE Trans. Very Large Scale Integr. Syst., 2021)

RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening. - Christos Georgakidis; Stavros Simoglou; Christos P. Sotiriou (DFT, 2022)

Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows. - Nikolaos Blias; Iordanis Lilitsis; Stavros Simoglou; Evangelos Bakas; Christos P. Sotiriou (VLSI-SoC, 2022)

Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops. - Nikolaos Chatzivangelis; Dimitris Valiantzas; Christos P. Sotiriou; Iordanis Lilitsis (VLSI-SoC, 2022)

Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis. - Christos Georgakidis; Dimitris Valiantzas; Stavros Simoglou; Iordanis Lilitsis; Nikolaos Chatzivangelis; Ilias Golfos; Marko S. Andjelkovic; Christos P. Sotiriou; Milos Krstic (DFT, 2023)

Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers. - Felipe A. Kuentzer; Christos Georgakidis; Christos P. Sotiriou; Milos Krstic (SBCCI, 2023)

Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model. - Stavros Simoglou; Iordanis Lilitsis; Nikolaos Blias; Christos P. Sotiriou (ISQED, 2024)

Swarm - A VLSI Timing, Fanout-aware Clustering Algorithm. - Christos P. Sotiriou; George Rafael Goudroumanis; Nikolaos Sketopoulos; Christos Georgakidis (ISQED, 2024)

Ternary Clock Tree Synthesis for 3D ICs. - Christos Pavlidis; Nikos Sketopoulos; Christos P. Sotiriou; Vasilis F. Pavlidis (SMACD, 2024)

Post-Placement Timing Optimisations on Asynchronous Designs. - Dimitrios Tsalapatas; Nikolaos Chatzivangelis; Christos P. Sotiriou; Nikolaos Sketopoulos (ASYNC, 2025)

Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT). - Marko S. Andjelkovic; Fabian Vargas 001; Milos Krstic; Luigi Dilillo; Alain Michez; Frederic Wrobel; Davide Bertozzi; Mikel Luján; Christos Georgakidis; Nikolaos Chatzivangelis; Katerina Tsilingiri; Nikolaos Zazatis; et al. (DATE, 2025)

3DPlace: Timing-driven Detailed Placement for Monolithic 3D ICs. - Dimitrios Vamvakidis; Christos Georgakidis; Aikaterini Tsilingiri; Nikolaos Sketopoulos; Christos P. Sotiriou; Vasilis F. Pavlidis (ISVLSI, 2025)

Prediction of Single Event Transient Propagation Using Machine Learning Models. - Marko S. Andjelkovic; Junchao Chen 001; Jelisaveta Aleksic; Vishnu Padmakumar; Milos Marjanovic; Nikolaos Zazatis; Trupti Ranjan Lenka; Danijel Dankovic; Christos P. Sotiriou; Fabian Vargas 001 (SMACD, 2025)