Christos P. Sotiriou
Orcid: 0000-0001-9318-474X
According to our database1,
Christos P. Sotiriou
authored at least 45 papers
between 2002 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance.
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Access, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020
2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2015
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
2013
Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
Consistent metagenes from cancer expression profiles yield agent specific predictors of chemotherapy response.
BMC Bioinform., 2011
BMC Bioinform., 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011
2008
Computational Intelligence in Clinical Oncology: Lessons Learned from an Analysis of a Clinical Study.
Proceedings of the Computational Intelligence in Biomedicine and Bioinformatics, 2008
A comparative study of survival models for breast cancer prognostication based on microarray data: does a single gene beat them all?
Bioinform., 2008
2007
Proceedings of the 44th Design Automation Conference, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
2005
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005
2004
Microprocess. Microsystems, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004
2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 40th Design Automation Conference, 2003
2002
Read, use, simulate, experiment and build: an integrated approach for teaching computer architecture.
Proceedings of the 2002 workshop on Computer architecture education, 2002
Proceedings of the 39th Design Automation Conference, 2002