Voltage references for ultra-low supply voltages. - Peter R. Kinget; Christos Vezyrtzis; Ed Chiang; B. Hung; T. L. Li (CICC, 2008)

Processing of Signals using Level-crossing Sampling. - Christos Vezyrtzis; Yannis P. Tsividis (ISCAS, 2009)

Direct processing of mpeg audio using companding and BFP techniques. - Christos Vezyrtzis; Aaron E. Klein; Dan Ellis; Yannis P. Tsividis (ICASSP, 2011)

Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications. - Christos Vezyrtzis; Yannis P. Tsividis; Steven M. Nowick (ICCD, 2012)

A flexible, clockless digital filter. - Christos Vezyrtzis; Weiwei Jiang 002; Steven M. Nowick; Yannis P. Tsividis (ESSCIRC, 2013)

Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques. - Christos Vezyrtzis (2013)

A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate. - Christos Vezyrtzis; Weiwei Jiang 002; Steven M. Nowick; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2014)

Resonant clock mega-mesh for the IBM z13TM. - David Shan; Phillip J. Restle; Doug Malone; Robert A. Groves; Eric Lai; Michael Koch 009; Jason Hibbeler; Yong Kim; Christos Vezyrtzis; Jan Feder; David Hogenmiller; Thomas J. Bucelot (VLSIC, 2015)

Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity. - Christos Vezyrtzis; Yannis P. Tsividis; Steven M. Nowick (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A statistical critical path monitor in 14nm CMOS. - Bruce M. Fleischer; Christos Vezyrtzis; Karthik Balakrishnan; Keith A. Jenkins (ICCD, 2016)

Very Low Voltage (VLV) Design. - Ramon Bertran; Pradip Bose; David M. Brooks; Jeff Burns; Alper Buyuktosunoglu; Nandhini Chandramoorthy; Eric Cheng; Martin Cochet; Schuyler Eldridge; Daniel Friedman; Hans M. Jacobson; Rajiv V. Joshi; et al. (ICCD, 2017)

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. - Eric Cheng; Jacob A. Abraham; Pradip Bose; Alper Buyuktosunoglu; Keith A. Campbell; Deming Chen; Chen-Yong Cher; Hyungmin Cho; Binh Q. Le; Klas Lilja; Shahrzad Mirkhani; Kevin Skadron; et al. (ICCD, 2017)

26.2 Power supply noise in a 22nm z13™ microprocessor. - Pierce I-Jen Chuang; Christos Vezyrtzis; Divya Pathak; Richard F. Rizzolo; Tobias Webel; Thomas Strach; Otto A. Torreiter; Preetham Lobo; Alper Buyuktosunoglu; Ramon Bertran; Michael S. Floyd; Malcolm S. Ware; et al. (ISSCC, 2017)

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. - Michael S. Floyd; Phillip J. Restle; Michael A. Sperling; Pawel Owczarczyk; Eric J. Fluhr; Joshua Friedrich; Paul Muench; Timothy Diemoz; Pierce Chuang; Christos Vezyrtzis (ISSCC, 2017)

Effect of HCI degradation on the variability of MOSFETS. - C. Zhou; Keith A. Jenkins; P. I. Chuang; Christos Vezyrtzis (IRPS, 2018)

Across the Stack Opportunities for Deep Learning Acceleration. - Vijayalakshmi Srinivasan; Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (ISLPED, 2018)

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor. - Christos Vezyrtzis; Thomas Strach; Pierce I-Jen Chuang; Preetham Lobo; Richard F. Rizzolo; Tobias Webel; Pawel Owczarczyk; Alper Buyuktosunoglu; Ramon Bertran; David T. Hui; Susan M. Eickhoff; Michael S. Floyd; et al. (ISSCC, 2018)

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. - Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Vijayalakshmi Srinivasan; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (VLSI Circuits, 2018)

IBM z14 design methodology enhancements in the 14-nm technology node. - Christopher J. Berry; James D. Warnock; John Badar; Dean G. Bair; Erwin Behnen; Brian Bell 001; Alper Buyuktosunoglu; Chris Cavitt; Pierce Chuang; Ofer Geva; Dina Hamid; John Isakson; et al. (IBM J. Res. Dev., 2018)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)

IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems. - Christopher J. Berry; David Wolpert 001; Christos Vezyrtzis; Richard F. Rizzolo; Sean M. Carey; Yaniv Maroz; Hunter F. Shi; Dureseti Chidambarrao; Christian Jacobi 002; Anthony Saporito; Thomas Strach; Alper Buyuktosunoglu; et al. (IEEE J. Solid State Circuits, 2019)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)