Efficient VLSI architecture for 2-D inverse discrete wavelet transforms. - Chu Yu; Sao-Jie Chen (ISCAS (3), 1999)

Design of an efficient VLSI architecture for 2-D discrete wavelet transforms. - Chu Yu; Sao-Jie Chen (IEEE Trans. Consumer Electron., 1999)

Determination of glottal closure instants by harmonic superposition. - Hwai-Tsu Hu; Shun-Ta Hsu; Chu Yu (Signal Process., 2003)

An efficient architecture for 2-D biorthogonal inverse discrete wavelet transforms. - Chu Yu (IEEE Trans. Consumer Electron., 2003)

Design and implantation of an ASIC architecture for 1.6 kbps speech synthesis. - Chu Yu; Hwai-Tsu Hu; Chen-Yen Lin (IEEE Trans. Consumer Electron., 2003)

A compact pipelined architecture with high-throughput for context-based binary arithmetic coding. - Chu Yu; Hwai-Tsu Hu (SoCC, 2007)

A 900 MHz to 5.2 GHz Dual-loop Feedback Multi-band LNA. - Jia-Wei Lin; Da-Tong Yen; Wei-Yi Hu; Chu Yu; Mao-Hsu Yen; Pao-Ann Hsiung; Sao-Jie Chen (ISCAS, 2009)

Parallel implementation of convolution encoder for software defined radio on DSP architecture. - Jui-Chieh Lin; Chu Yu; Mao-Hsu Yen; Pao-Ann Hsiung; Sao-Jie Chen; Yu Hen Hu (ICSAMOS, 2009)

An instruction set architecture independent design method for embedded OFDM-based software defined transmitter. - Jui-Chieh Lin; Minja Hsieh; Ming-Jung Fan-Chiang; Chu Yu; Sao-Jie Chen; Yu Hen Hu (SoCC, 2009)

Combining HMM and Weighted Deviation Linear Transformation for Highband Speech Parameter Estimation. - Hwai-Tsu Hu; Chu Yu (IEICE Trans. Inf. Syst., 2009)

Perfect shuffling for cycle efficient puncturer and interleaver for software defined radio. - Jui-Chieh Lin; Minja Hsieh; Ming-Jung Fan-Chiang; Song-Yen Mao; Chu Yu; Sao-Jie Chen; Yu Hen Hu (ISCAS, 2010)

ARAL-CR: An adaptive reasoning and learning cognitive radio platform. - Sao-Jie Chen; Pao-Ann Hsiung; Chu Yu; Mao-Hsu Yen; Sakir Sezer; Michael J. Schulte; Yu Hen Hu (ICSAMOS, 2010)

Low power design of phase-change memory based on a comprehensive model. - Meng-Hsueh Chiang; Yi-Bo Liao; Jun-Tin Lin; Wei-Chou Hsu; Chu Yu; Pei-Chia Chiang; Y.-Y. Hsu; W.-H. Liu; Shyh-Shyuan Sheu; Keng-Li Su; Ming-Jer Kao; Ming-Jinn Tsai (IET Comput. Digit. Tech., 2010)

A low-power 64-point pipeline FFT/IFFT processor for OFDM applications. - Chu Yu; Mao-Hsu Yen; Pao-Ann Hsiung; Sao-Jie Chen (IEEE Trans. Consumer Electron., 2011)

A Ubiquitous Scheme for a One-to-Many Switching Tunnel for Healthcare Utilization. - Po-Hsun Cheng; Shun-Hsiang Hu; Yu-Pao Lin; Hsiao-Chi Hsieh; Bor-Shing Lin; Chu Yu; Sao-Jie Chen (CICSyN, 2012)

Design of a low-power OFDM baseband receiver for wireless communications. - Chu Yu; Chien-Hung Kuo; Chen-Hen Sung; Mao-Hsu Yen; Sao-Jie Chen (ICCE, 2012)

A Perceptually Adaptive QIM Scheme for Efficient Watermark Synchronization. - Hwai-Tsu Hu; Chu Yu (IEICE Trans. Inf. Syst., 2012)

A HMM-WDLT framework for HNM-based voice conversion with parametric adjustment in formant bandwidth, duration and excitation. - Hwai-Tsu Hu; Chu Yu (Int. J. Speech Technol., 2012)

Design and implementation of a low-power OFDM receiver for wireless communications. - Chu Yu; Chen-Hen Sung; Chien-Hung Kuo; Mao-Hsu Yen; Sao-Jie Chen (IEEE Trans. Consumer Electron., 2012)

Hyper-Universal Switch Network for FPIC Design. - Mao-Hsu Yen; Chu Yu; Yih-Hsia Lin; Chang-Hsien Chung (CISIS, 2013)

A 128/512/1024/2048-point pipeline FFT/IFFT architecture for mobile WiMAX. - Chu Yu (GCCE, 2013)

A dual-code-rate memoryless Viterbi decoder for wireless communication systems. - Chu Yu; Yu-Shan Su; Bor-Shing Lin; Po-Hsun Cheng; Sao-Jie Chen (ICCE, 2013)

Design of a (255, 239) Reed-Solomon decoder using a simplified step-by-step algorithm. - Yu-Shan Su; Chu Yu; Bor-Shing Lin; Po-Hsun Cheng; Sao-Jie Chen (ISCE, 2013)

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design. - Mao-Hsu Yen; Chu Yu; Horng-Ru Liao; Chin-Fa Hsieh (VLSI Design, 2013)

Improvement on a block-serial fully-overlapped QC-LDPC decoder for IEEE 802.11n. - Chu Yu; Ho-Sheng Chuang; Bor-Shing Lin; Po-Hsun Cheng; Sao-Jie Chen (ICCE, 2014)

Incorporation of perceptually adaptive QIM with singular value decomposition for blind audio watermarking. - Hwai-Tsu Hu; Hsien-Hsin Chou; Chu Yu; Ling-Yuan Hsu (EURASIP J. Adv. Signal Process., 2014)

Efficient image denoising scheme for removal of impulse noise. - Li-Zhon Hou; Chien-Feng Kuo; Zhi-Hong Lin; Chu Yu (GCCE, 2015)

An effective spatial-temporal denoising approach for depth images. - Bor-Shing Lin; Wei-Ren Chou; Chu Yu; Po-Hsun Cheng; Po-Jui Tseng; Sao-Jie Chen (DSP, 2015)

Variable code length soft-output decoder of polar codes. - Jung-Hong Po; Sao-Jie Chen; Chu Yu (DSP, 2015)

Comment on "On Optimal Hyperuniversal and Rearrangeable Switch Box Designs". - Mao-Hsu Yen; Hung-Kuan Yen; Chu Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Two-Mode Reed-Solomon Decoder Using A Simplified Step-by-Step Algorithm. - Chu Yu; Yu-Shan Su (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems. - Chu Yu; Mao-Hsu Yen (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Lower bit-error-rate polar-LDPC concatenated coding for wireless communication systems. - Chu Yu; Zhi-Hong Lin; Ting-Wei Hsu; Mao-Wen Chen; Yi-An Chen (GCCE, 2017)

Low-complexity twiddle factor generator for FFT processors. - Chu Yu; Kuang-Hsiao Lee; Chien-Feng Kuo (ICCE, 2017)

Three-Parallel Reed-Solomon Decoder using a Simplified Step-by-Step Algorithm. - Chu Yu; Kuang-Hsiao Lee; Jin-Yu Chen; Mao-Wen Chen; Yi-An Chen (GCCE, 2018)

Peer Group and Hybrid Vector Filter for Removal of Impulse Noise in Color Images. - Chu Yu; Mao-Wen Chen; Jin-Yu Chen; Jia-Hong Tang (ICCE-TW, 2019)

Friendly Appearance of Multiple Secret Sharing. - Heri Prasetyo; Chih-Hsien Hsia; Chu Yu; Albertus Ricky Wirawan (ICCE-TW, 2020)

Realization of a Real-Time Image Denoising System for Dashboard Camera Applications. - Chu Yu; Li-Zhong Hou (IEEE Trans. Consumer Electron., 2022)

Efficient Max Pooling Architecture with Zero-Padding for Convolutional Neural Networks. - Chu Yu; Po-Hao Hung; Jing-Huan Hong; Han-Yu Chiang (GCCE, 2023)

Generic Hardware Integrating Multiple Activation Functions for Deep Learning Applications. - Chu Yu; Yi-Ching Hung (ICCE-Taiwan, 2024)